175 lines
4.1 KiB
C
175 lines
4.1 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/platform.h>
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#include <gpc.h>
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#include <imx_aipstz.h>
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#include <imx_uart.h>
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#include <imx_rdc.h>
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#include <imx8m_caam.h>
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#include <plat_imx8.h>
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static const mmap_region_t imx_mmap[] = {
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MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
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MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
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{0},
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};
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static const struct aipstz_cfg aipstz[] = {
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{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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static const struct imx_rdc_cfg rdc[] = {
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/* Master domain assignment */
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RDC_MDAn(0x1, DID1),
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/* peripherals domain permission */
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/* memory region */
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/* Sentinel */
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{0},
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};
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/* get SPSR for BL33 entry */
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl31_tzc380_setup(void)
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{
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unsigned int val;
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val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
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if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
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return;
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tzc380_init(IMX_TZASC_BASE);
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/*
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* Need to substact offset 0x40000000 from CPU address when
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* programming tzasc region for i.mx8mm.
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*/
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/* Enable 1G-5G S/NS RW */
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tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
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TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_uart_t console;
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int i;
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/* Enable CSU NS access permission */
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for (i = 0; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
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}
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imx_aipstz_init(aipstz);
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imx_rdc_init(rdc);
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imx8m_caam_init();
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console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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/* This console is only used for boot stage */
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console_set_scope(&console.console, CONSOLE_FLAG_BOOT);
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/*
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* tell BL3-1 where the non-secure software image is located
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* and the entry state information.
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*/
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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bl31_tzc380_setup();
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}
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void bl31_plat_arch_setup(void)
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{
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mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
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MT_MEMORY | MT_RO | MT_SECURE);
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#if USE_COHERENT_MEM
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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mmap_add(imx_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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/* select the CKIL source to 32K OSC */
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mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
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plat_gic_driver_init();
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plat_gic_init();
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imx_gpc_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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return &bl32_image_ep_info;
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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