71 lines
1.4 KiB
ArmAsm
71 lines
1.4 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cortex_a53.h>
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#include <hi6220.h>
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#include <hisi_sram_map.h>
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.global pm_asm_code
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.global pm_asm_code_end
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.global v7_asm
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.global v7_asm_end
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func pm_asm_code _align=3
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mov x0, 0
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msr oslar_el1, x0
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mrs x0, CORTEX_A53_CPUACTLR_EL1
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bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
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CORTEX_A53_CPUACTLR_EL1_L1RADIS)
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orr x0, x0, #0x180000
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orr x0, x0, #0xe000
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msr CORTEX_A53_CPUACTLR_EL1, x0
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mrs x3, actlr_el3
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orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
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msr actlr_el3, x3
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mrs x3, actlr_el2
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orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT
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msr actlr_el2, x3
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ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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pen: ldr x4, [x3, x0, LSL #3]
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cbz x4, pen
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mov x0, #0x0
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mov x1, #0x0
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mov x2, #0x0
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mov x3, #0x0
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br x4
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.ltorg
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pm_asm_code_end:
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endfunc pm_asm_code
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/*
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* By default, all cores in Hi6220 reset with aarch32 mode.
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* Now hardcode ARMv7 instructions to execute warm reset for
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* switching aarch64 mode.
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*/
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.align 3
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.section .rodata.v7_asm, "aS"
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v7_asm:
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.word 0xE1A00000 // nop
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.word 0xE3A02003 // mov r2, #3
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.word 0xEE0C2F50 // mcr 15, 0, r2, cr12, cr0, {2}
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.word 0xE320F003 // wfi
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.ltorg
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v7_asm_end:
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