119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
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#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
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#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
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#define mpidr_is_valid(mpidr) ( \
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MPIDR_AFFLVL3_VAL(mpidr) == 0 && \
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MPIDR_AFFLVL2_VAL(mpidr) == 0 && \
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MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \
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MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER)
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static int sunxi_pwr_domain_on(u_register_t mpidr)
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{
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if (mpidr_is_valid(mpidr) == 0)
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return PSCI_E_INTERN_FAIL;
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sunxi_cpu_on(mpidr);
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return PSCI_E_SUCCESS;
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}
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static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
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{
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gicv2_cpuif_disable();
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}
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static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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sunxi_cpu_off(read_mpidr());
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while (1)
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wfi();
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}
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static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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static void __dead2 sunxi_system_off(void)
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{
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/* Turn off all secondary CPUs */
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sunxi_disable_secondary_cpus(read_mpidr());
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sunxi_power_down();
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}
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static void __dead2 sunxi_system_reset(void)
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{
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/* Reset the whole system when the watchdog times out */
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mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
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/* Enable the watchdog with the shortest timeout (0.5 seconds) */
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mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
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/* Wait for twice the watchdog timeout before panicking */
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mdelay(1000);
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ERROR("PSCI: System reset failed\n");
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wfi();
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panic();
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}
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static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entry point must be in DRAM */
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if (ns_entrypoint >= SUNXI_DRAM_BASE)
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return PSCI_E_SUCCESS;
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return PSCI_E_INVALID_ADDRESS;
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}
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static plat_psci_ops_t sunxi_psci_ops = {
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.pwr_domain_on = sunxi_pwr_domain_on,
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.pwr_domain_off = sunxi_pwr_domain_off,
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.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi,
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.pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
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.system_off = sunxi_system_off,
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.system_reset = sunxi_system_reset,
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.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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assert(psci_ops);
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for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
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mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
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sec_entrypoint & 0xffffffff);
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mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
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sec_entrypoint >> 32);
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}
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*psci_ops = &sunxi_psci_ops;
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return 0;
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}
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