124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <plat/common/platform.h>
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#include <core_off_arisc.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
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{
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
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return;
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VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
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}
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static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
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{
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
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return;
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VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
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/* Power enable sequence from original Allwinner sources */
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
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}
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void sunxi_cpu_off(u_register_t mpidr)
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{
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unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
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/* Deassert DBGPWRDUP */
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mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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/* We can't turn ourself off like this, but it works for other cores. */
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if (read_mpidr() != mpidr) {
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/* Activate the core output clamps, but not for core 0. */
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if (core != 0)
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mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
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BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Remove power from the CPU */
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sunxi_cpu_disable_power(cluster, core);
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return;
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}
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/* Simplifies assembly, all SoCs so far are single cluster anyway. */
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assert(cluster == 0);
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/*
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* If we are supposed to turn ourself off, tell the arisc SCP
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* to do that work for us. The code expects the core mask to be
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* patched into the first instruction.
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*/
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sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
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0, BIT_32(core));
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}
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void sunxi_cpu_on(u_register_t mpidr)
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{
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unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
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/* Assert CPU core reset */
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mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Set CPU to start in AArch64 mode */
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mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core));
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/* Apply power to the CPU */
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sunxi_cpu_enable_power(cluster, core);
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/* Release the core output clamps */
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mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
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/* Deassert CPU power-on reset */
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mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Deassert CPU core reset */
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mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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/* Assert DBGPWRDUP */
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mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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}
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void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
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{
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unsigned int cluster;
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unsigned int core;
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for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) {
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for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) {
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u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) |
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(core << MPIDR_AFF0_SHIFT) |
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BIT(31);
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if (mpidr != primary_mpidr)
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sunxi_cpu_off(mpidr);
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}
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}
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}
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