116 lines
4.4 KiB
ArmAsm
116 lines
4.4 KiB
ArmAsm
# turn_off_core.S
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#
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# Copyright (c) 2018, Andre Przywara <osp@andrep.de>
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# OpenRISC assembly to turn off an ARM core on an Allwinner SoC from
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# the arisc management controller.
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# Generate a binary representation with:
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# $ or1k-elf-as -c -o turn_off_core.o turn_off_core.S
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# $ or1k-elf-objcopy -O binary --reverse-bytes=4 turn_off_core.o \
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# turn_off_core.bin
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# The encoded instructions go into an array defined in
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# plat/allwinner/sun50i_*/include/core_off_arisc.h, to be handed off to
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# the arisc processor.
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#
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# This routine is meant to be called directly from arisc reset (put the
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# start address in the reset vector), to be actually triggered by that
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# very ARM core to be turned off.
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# It expects the core number presented as a mask in the upper half of
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# r3, so to be patched in the lower 16 bits of the first instruction,
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# overwriting the 0 in this code here.
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# The code will do the following:
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# - Read the C_CPU_STATUS register, which contains the status of the WFI
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# lines of each of the four A53 cores.
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# - Loop until the core in question reaches WFI.
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# - Using that mask, activate the core output clamps by setting the
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# respective core bit in CPUX_PWROFF_GATING_REG (0x1f01500).
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# Note that the clamp for core 0 covers more than just the core, activating
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# it hangs the whole system. So we skip this step for core 0.
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# - Using the negated mask, assert the core's reset line by clearing the
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# respective bit in C_RST_CTRL (0x1f01c30).
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# - Finally turn off the core's power switch by writing 0xff to the
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# respective CPUx_PWR_SWITCH_REG (0x1f01540 ff.)
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# - Assert the arisc's own reset to end execution.
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# This also signals other arisc users that the chip is free again.
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# So in C this would look like:
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# while (!(readl(0x1700030) & (1U << core_nr)))
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# ;
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# if (core_nr != 0)
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# writel(readl(0x1f01500) | (1U << core_nr), 0x1f01500);
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# writel(readl(0x1f01c30) & ~(1U << core_nr), 0x1f01c30);
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# writel(0xff, 0x1f01540 + (core_nr * 4));
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# (using A64/H5 addresses)
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.text
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_start:
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l.movhi r3, 0 # FIXUP! with core mask
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l.movhi r0, 0 # clear r0
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l.movhi r13, 0x170 # r13: CPU_CFG_BASE=0x01700000
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wait_wfi:
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l.lwz r5, 0x30(r13) # load C_CPU_STATUS
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l.and r5, r5, r3 # mask requested core
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l.sfeq r5, r0 # is it not yet in WFI?
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l.bf wait_wfi # try again
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l.srli r6, r3, 16 # move mask to lower 16 bits
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l.sfeqi r6, 1 # core 0 is special
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l.bf 1f # don't touch the bit for core 0
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l.movhi r13, 0x1f0 # address of R_CPUCFG (delay)
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l.lwz r5, 0x1500(r13) # core output clamps
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l.or r5, r5, r6 # set bit to ...
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l.sw 0x1500(r13), r5 # ... activate for our core
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1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
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l.xori r6, r6, -1 # negate core mask
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l.and r5, r5, r6 # clear bit to ...
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l.sw 0x1c30(r13), r5 # ... assert for our core
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l.ff1 r6, r3 # get core number from high mask
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l.addi r6, r6, -17 # convert to 0-3
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l.slli r6, r6, 2 # r5: core number*4 (0-12)
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l.add r6, r6, r13 # add to base address
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l.ori r5, r0, 0xff # 0xff means all switches off
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l.sw 0x1540(r6), r5 # core power switch registers
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reset: l.sw 0x1c00(r13),r0 # pull down our own reset line
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l.j reset # just in case ....
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l.nop 0x0 # (delay slot)
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# same as above, but with the MMIO addresses matching the H6 SoC
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_start_h6:
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l.movhi r3, 0 # FIXUP! with core mask
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l.movhi r0, 0 # clear r0
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l.movhi r13, 0x901 # r13: CPU_CFG_BASE=0x09010000
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1:
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l.lwz r5, 0x80(r13) # load C_CPU_STATUS
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l.and r5, r5, r3 # mask requested core
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l.sfeq r5, r0 # is it not yet in WFI?
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l.bf 1b # try again
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l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
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l.sfeqi r6, 1 # core 0 is special
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l.bf 1f # don't touch the bit for core 0
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l.movhi r13, 0x700 # address of R_CPUCFG (ds)
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l.lwz r5, 0x0444(r13) # core output clamps
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l.or r5, r5, r6 # set bit to ...
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l.sw 0x0444(r13), r5 # ... activate for our core
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1: l.lwz r5, 0x0440(r13) # CPU power-on reset
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l.xori r6, r6, -1 # negate core mask
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l.and r5, r5, r6 # clear bit to ...
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l.sw 0x0440(r13), r5 # ... assert for our core
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l.ff1 r6, r3 # get core number from high mask
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l.addi r6, r6, -17 # convert to 0-3
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l.slli r6, r6, 2 # r5: core number*4 (0-12)
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l.add r6, r6, r13 # add to base address
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l.ori r5, r0, 0xff # 0xff means all switches off
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l.sw 0x0450(r6), r5 # core power switch registers
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1: l.sw 0x0400(r13),r0 # pull down our own reset line
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l.j 1b # just in case ...
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l.nop 0x0 # (delay slot)
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