262 lines
7.2 KiB
C
262 lines
7.2 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RAS_ARCH_H
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#define RAS_ARCH_H
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/*
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* Size of nodes implementing Standard Error Records - currently only 4k is
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* supported.
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*/
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#define STD_ERR_NODE_SIZE_NUM_K 4U
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/*
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* Individual register offsets within an error record in Standard Error Record
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* format when error records are accessed through memory-mapped registers.
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*/
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#define ERR_FR(n) (0x0ULL + (64ULL * (n)))
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#define ERR_CTLR(n) (0x8ULL + (64ULL * (n)))
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#define ERR_STATUS(n) (0x10ULL + (64ULL * (n)))
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#define ERR_ADDR(n) (0x18ULL + (64ULL * (n)))
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#define ERR_MISC0(n) (0x20ULL + (64ULL * (n)))
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#define ERR_MISC1(n) (0x28ULL + (64ULL * (n)))
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/* Group Status Register (ERR_STATUS) offset */
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#define ERR_GSR(base, size_num_k, n) \
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((base) + (0x380ULL * (size_num_k)) + (8ULL * (n)))
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/* Management register offsets */
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#define ERR_DEVID(base, size_num_k) \
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((base) + ((0x400ULL * (size_num_k)) - 0x100ULL) + 0xc8ULL)
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#define ERR_DEVID_MASK 0xffffUL
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/* Standard Error Record status register fields */
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#define ERR_STATUS_AV_SHIFT 31
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#define ERR_STATUS_AV_MASK U(0x1)
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#define ERR_STATUS_V_SHIFT 30
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#define ERR_STATUS_V_MASK U(0x1)
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#define ERR_STATUS_UE_SHIFT 29
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#define ERR_STATUS_UE_MASK U(0x1)
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#define ERR_STATUS_ER_SHIFT 28
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#define ERR_STATUS_ER_MASK U(0x1)
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#define ERR_STATUS_OF_SHIFT 27
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#define ERR_STATUS_OF_MASK U(0x1)
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#define ERR_STATUS_MV_SHIFT 26
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#define ERR_STATUS_MV_MASK U(0x1)
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#define ERR_STATUS_CE_SHIFT 24
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#define ERR_STATUS_CE_MASK U(0x3)
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#define ERR_STATUS_DE_SHIFT 23
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#define ERR_STATUS_DE_MASK U(0x1)
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#define ERR_STATUS_PN_SHIFT 22
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#define ERR_STATUS_PN_MASK U(0x1)
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#define ERR_STATUS_UET_SHIFT 20
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#define ERR_STATUS_UET_MASK U(0x3)
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#define ERR_STATUS_IERR_SHIFT 8
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#define ERR_STATUS_IERR_MASK U(0xff)
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#define ERR_STATUS_SERR_SHIFT 0
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#define ERR_STATUS_SERR_MASK U(0xff)
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#define ERR_STATUS_GET_FIELD(_status, _field) \
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(((_status) >> ERR_STATUS_ ##_field ##_SHIFT) & ERR_STATUS_ ##_field ##_MASK)
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#define ERR_STATUS_CLR_FIELD(_status, _field) \
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(_status) &= ~(ERR_STATUS_ ##_field ##_MASK << ERR_STATUS_ ##_field ##_SHIFT)
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#define ERR_STATUS_SET_FIELD(_status, _field, _value) \
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(_status) |= (((_value) & ERR_STATUS_ ##_field ##_MASK) << ERR_STATUS_ ##_field ##_SHIFT)
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#define ERR_STATUS_WRITE_FIELD(_status, _field, _value) do { \
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ERR_STATUS_CLR_FIELD(_status, _field, _value); \
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ERR_STATUS_SET_FIELD(_status, _field, _value); \
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} while (0)
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/* Standard Error Record control register fields */
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#define ERR_CTLR_WDUI_SHIFT 11
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#define ERR_CTLR_WDUI_MASK 0x1
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#define ERR_CTLR_RDUI_SHIFT 10
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#define ERR_CTLR_RDUI_MASK 0x1
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#define ERR_CTLR_DUI_SHIFT ERR_CTLR_RDUI_SHIFT
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#define ERR_CTLR_DUI_MASK ERR_CTLR_RDUI_MASK
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#define ERR_CTLR_WCFI_SHIFT 9
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#define ERR_CTLR_WCFI_MASK 0x1
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#define ERR_CTLR_RCFI_SHIFT 8
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#define ERR_CTLR_RCFI_MASK 0x1
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#define ERR_CTLR_CFI_SHIFT ERR_CTLR_RCFI_SHIFT
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#define ERR_CTLR_CFI_MASK ERR_CTLR_RCFI_MASK
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#define ERR_CTLR_WUE_SHIFT 7
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#define ERR_CTLR_WUE_MASK 0x1
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#define ERR_CTLR_WFI_SHIFT 6
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#define ERR_CTLR_WFI_MASK 0x1
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#define ERR_CTLR_WUI_SHIFT 5
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#define ERR_CTLR_WUI_MASK 0x1
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#define ERR_CTLR_RUE_SHIFT 4
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#define ERR_CTLR_RUE_MASK 0x1
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#define ERR_CTLR_UE_SHIFT ERR_CTLR_RUE_SHIFT
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#define ERR_CTLR_UE_MASK ERR_CTLR_RUE_MASK
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#define ERR_CTLR_RFI_SHIFT 3
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#define ERR_CTLR_RFI_MASK 0x1
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#define ERR_CTLR_FI_SHIFT ERR_CTLR_RFI_SHIFT
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#define ERR_CTLR_FI_MASK ERR_CTLR_RFI_MASK
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#define ERR_CTLR_RUI_SHIFT 2
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#define ERR_CTLR_RUI_MASK 0x1
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#define ERR_CTLR_UI_SHIFT ERR_CTLR_RUI_SHIFT
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#define ERR_CTLR_UI_MASK ERR_CTLR_RUI_MASK
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#define ERR_CTLR_ED_SHIFT 0
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#define ERR_CTLR_ED_MASK 0x1
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#define ERR_CTLR_CLR_FIELD(_ctlr, _field) \
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(_ctlr) &= ~(ERR_CTLR_ ##_field _MASK << ERR_CTLR_ ##_field ##_SHIFT)
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#define ERR_CTLR_SET_FIELD(_ctlr, _field, _value) \
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(_ctlr) |= (((_value) & ERR_CTLR_ ##_field ##_MASK) << ERR_CTLR_ ##_field ##_SHIFT)
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#define ERR_CTLR_ENABLE_FIELD(_ctlr, _field) \
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ERR_CTLR_SET_FIELD(_ctlr, _field, ERR_CTLR_ ##_field ##_MASK)
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/* Uncorrected error types for Asynchronous exceptions */
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#define ERROR_STATUS_UET_UC 0x0 /* Uncontainable */
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#define ERROR_STATUS_UET_UEU 0x1 /* Unrecoverable */
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#define ERROR_STATUS_UET_UEO 0x2 /* Restable */
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#define ERROR_STATUS_UET_UER 0x3 /* Recoverable */
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/* Error types for Synchronous exceptions */
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#define ERROR_STATUS_SET_UER 0x0 /* Recoverable */
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#define ERROR_STATUS_SET_UEO 0x1 /* Restable */
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#define ERROR_STATUS_SET_UC 0x2 /* Uncontainable */
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#define ERROR_STATUS_SET_CE 0x3 /* Corrected */
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/* Implementation Defined Syndrome bit in ESR */
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#define SERROR_IDS_BIT U(24)
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/*
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* Asynchronous Error Type in exception syndrome. The field has same values in
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* both DISR_EL1 and ESR_EL3 for SError.
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*/
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#define EABORT_AET_SHIFT U(10)
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#define EABORT_AET_WIDTH U(3)
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#define EABORT_AET_MASK U(0x7)
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/* DFSC field in Asynchronous exception syndrome */
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#define EABORT_DFSC_SHIFT U(0)
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#define EABORT_DFSC_WIDTH U(6)
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#define EABORT_DFSC_MASK U(0x3f)
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/* Synchronous Error Type in exception syndrome. */
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#define EABORT_SET_SHIFT U(11)
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#define EABORT_SET_WIDTH U(2)
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#define EABORT_SET_MASK U(0x3)
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/* DFSC code for SErrors */
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#define DFSC_SERROR 0x11
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/* I/DFSC code for synchronous external abort */
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#define SYNC_EA_FSC 0x10
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#ifndef __ASSEMBLER__
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <context.h>
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#include <lib/mmio.h>
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#include <stdint.h>
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/*
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* Standard Error Record accessors for memory-mapped registers.
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*/
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static inline uint64_t ser_get_feature(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_FR(idx));
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}
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static inline uint64_t ser_get_control(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_CTLR(idx));
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}
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static inline uint64_t ser_get_status(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_STATUS(idx));
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}
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/*
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* Error handling agent would write to the status register to clear an
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* identified/handled error. Most fields in the status register are
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* conditional write-one-to-clear.
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*
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* Typically, to clear the status, it suffices to write back the same value
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* previously read. However, if there were new, higher-priority errors recorded
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* on the node since status was last read, writing read value won't clear the
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* status. Therefore, an error handling agent must wait on and verify the status
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* has indeed been cleared.
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*/
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static inline void ser_set_status(uintptr_t base, unsigned int idx,
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uint64_t status)
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{
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mmio_write_64(base + ERR_STATUS(idx), status);
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}
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static inline uint64_t ser_get_addr(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_ADDR(idx));
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}
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static inline uint64_t ser_get_misc0(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_MISC0(idx));
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}
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static inline uint64_t ser_get_misc1(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_MISC1(idx));
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}
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/*
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* Standard Error Record helpers for System registers.
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*/
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static inline void ser_sys_select_record(unsigned int idx)
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{
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unsigned int max_idx __unused =
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(unsigned int) read_erridr_el1() & ERRIDR_MASK;
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assert(idx < max_idx);
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write_errselr_el1(idx);
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isb();
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}
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/* Library functions to probe Standard Error Record */
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int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data);
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int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data);
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#endif /* __ASSEMBLER__ */
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#endif /* RAS_ARCH_H */
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