572 lines
16 KiB
C
572 lines
16 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <cortex_a57.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <bpmp.h>
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#include <flowctrl.h>
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#include <lib/utils.h>
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#include <memctrl.h>
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#include <pmc.h>
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#include <platform_def.h>
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#include <security_engine.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#include <tegra_platform.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16).
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*/
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#define CPU_CMPLX_RESET_CLR 0x454
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#define CPU_CORE_RESET_MASK 0x10001
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/* Clock and Reset controller registers for system clock's settings */
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#define SCLK_RATE 0x30
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#define SCLK_BURST_POLICY 0x28
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#define SCLK_BURST_POLICY_DEFAULT 0x10000000
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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static bool tegra_bpmp_available = true;
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int state_id = psci_get_pstate_id(power_state);
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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/* Sanity check the requested state id */
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switch (state_id) {
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case PSTATE_ID_CORE_POWERDN:
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/*
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* Core powerdown request only for afflvl 0
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*/
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff;
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break;
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case PSTATE_ID_CLUSTER_IDLE:
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/*
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* Cluster idle request for afflvl 0
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*/
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
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break;
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case PSTATE_ID_SOC_POWERDN:
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/*
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* sc7entry-fw must be present in the system when the bpmp
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* firmware is not present, for a successful System Suspend
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* entry.
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*/
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if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base)
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return PSCI_E_NOT_SUPPORTED;
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/*
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* System powerdown request only for afflvl 2
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*/
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for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
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PLAT_SYS_SUSPEND_STATE_ID;
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break;
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default:
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ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
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return PSCI_E_INVALID_PARAMS;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level.
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******************************************************************************/
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plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *states,
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unsigned int ncpu)
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{
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plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
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int cpu = plat_my_core_pos();
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int core_pos = read_mpidr() & MPIDR_CPU_MASK;
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uint32_t bpmp_reply, data[3], val;
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int ret;
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/* get the power state at this level */
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if (lvl == MPIDR_AFFLVL1)
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target = *(states + core_pos);
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if (lvl == MPIDR_AFFLVL2)
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target = *(states + cpu);
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if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) {
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/* initialize the bpmp interface */
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ret = tegra_bpmp_init();
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if (ret != 0U) {
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/*
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* flag to indicate that BPMP firmware is not
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* available and the CPU has to handle entry/exit
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* for all power states
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*/
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tegra_bpmp_available = false;
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/* Cluster idle not allowed */
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target = PSCI_LOCAL_STATE_RUN;
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/*******************************************
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* BPMP is not present, so handle CC6 entry
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* from the CPU
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******************************************/
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/* check if cluster idle state has been enabled */
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val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL);
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if (val == ENABLE_CLOSED_LOOP) {
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/*
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* Acquire the cluster idle lock to stop
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* other CPUs from powering up.
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*/
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tegra_fc_ccplex_pgexit_lock();
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/* Cluster idle only from the last standing CPU */
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if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) {
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/* Cluster idle allowed */
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target = PSTATE_ID_CLUSTER_IDLE;
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} else {
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/* release cluster idle lock */
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tegra_fc_ccplex_pgexit_unlock();
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}
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}
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} else {
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/* Cluster power-down */
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data[0] = (uint32_t)cpu;
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data[1] = TEGRA_PM_CC6;
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data[2] = TEGRA_PM_SC1;
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ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
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(void *)&data, (int)sizeof(data),
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(void *)&bpmp_reply,
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(int)sizeof(bpmp_reply));
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/* check if cluster power down is allowed */
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if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
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/* Cluster power down not allowed */
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target = PSCI_LOCAL_STATE_RUN;
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}
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}
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} else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
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(target == PSTATE_ID_SOC_POWERDN)) {
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/* System Suspend */
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target = PSTATE_ID_SOC_POWERDN;
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} else {
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; /* do nothing */
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}
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return target;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr();
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const plat_local_state_t *pwr_domain_state =
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target_state->pwr_domain_state;
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unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2];
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unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1];
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unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0];
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uint32_t cfg;
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int ret = PSCI_E_SUCCESS;
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uint32_t val;
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) ||
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(stateid_afflvl0 == PSTATE_ID_SOC_POWERDN));
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assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) ||
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(stateid_afflvl1 == PSTATE_ID_SOC_POWERDN));
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if (tegra_chipid_is_t210_b01()) {
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/* Suspend se/se2 and pka1 */
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if (tegra_se_suspend() != 0) {
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ret = PSCI_E_INTERN_FAIL;
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}
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}
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} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) {
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assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN);
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if (!tegra_bpmp_available) {
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/*
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* When disabled, DFLL loses its state. Enable
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* open loop state for the DFLL as we dont want
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* garbage values being written to the pmic
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* when we enter cluster idle state.
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*/
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mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
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ENABLE_OPEN_LOOP);
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/* Find if the platform uses OVR2/MAX77621 PMIC */
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cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
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if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
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/* OVR2 */
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/* PWM tristate */
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val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
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val |= PINMUX_PWM_TRISTATE;
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mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
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/*
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* SCRATCH201[1] is being used to identify CPU
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* PMIC in warmboot code.
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* 0 : OVR2
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* 1 : MAX77621
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*/
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tegra_pmc_write_32(PMC_SCRATCH201, 0x0);
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} else {
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/* MAX77621 */
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tegra_pmc_write_32(PMC_SCRATCH201, 0x2);
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}
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}
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/* Prepare for cluster idle */
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tegra_fc_cluster_idle(mpidr);
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} else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
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/* Prepare for cpu powerdn */
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tegra_fc_cpu_powerdn(mpidr);
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} else {
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ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__,
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stateid_afflvl2, stateid_afflvl1, stateid_afflvl0);
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ret = PSCI_E_NOT_SUPPORTED;
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}
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return ret;
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}
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static void tegra_reset_all_dma_masters(void)
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{
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uint32_t val, mask;
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/*
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* Reset all possible DMA masters in the system.
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*/
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val = GPU_RESET_BIT;
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val);
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val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
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NVJPG_RESET_BIT | NVDEC_RESET_BIT;
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val);
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val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
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VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
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SDMMC2_RESET_BIT;
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val);
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val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val);
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val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
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PCIE_RESET_BIT | SDMMC3_RESET_BIT;
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val);
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val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val);
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/*
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* If any of the DMA masters are still alive, assume
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* that the system has been compromised and reboot.
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*/
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
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mask = GPU_RESET_BIT;
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if ((val & mask) != mask)
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tegra_pmc_system_reset();
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mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
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NVJPG_RESET_BIT | NVDEC_RESET_BIT;
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y);
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if ((val & mask) != mask)
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tegra_pmc_system_reset();
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mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
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VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
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SDMMC2_RESET_BIT;
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L);
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if ((val & mask) != mask)
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tegra_pmc_system_reset();
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mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H);
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if ((val & mask) != mask)
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tegra_pmc_system_reset();
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mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
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PCIE_RESET_BIT | SDMMC3_RESET_BIT;
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U);
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if ((val & mask) != mask)
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tegra_pmc_system_reset();
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V);
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mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
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if ((val & mask) != mask)
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tegra_pmc_system_reset();
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}
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int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr();
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const plat_local_state_t *pwr_domain_state =
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target_state->pwr_domain_state;
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unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL];
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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uint32_t val;
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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if (tegra_chipid_is_t210_b01()) {
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/* Save tzram contents */
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tegra_se_save_tzram();
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}
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/* de-init the interface */
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tegra_bpmp_suspend();
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/*
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* The CPU needs to load the System suspend entry firmware
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* if nothing is running on the BPMP.
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*/
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if (!tegra_bpmp_available) {
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/*
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* BPMP firmware is not running on the co-processor, so
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* we need to explicitly load the firmware to enable
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* entry/exit to/from System Suspend and set the BPMP
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* on its way.
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*/
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/* Power off BPMP before we proceed */
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tegra_fc_bpmp_off();
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/* bond out IRAM banks B, C and D */
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U,
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IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT |
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IRAM_D_LOCK_BIT);
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/* bond out APB/AHB DMAs */
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H,
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APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT);
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/* Power off BPMP before we proceed */
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tegra_fc_bpmp_off();
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/*
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* Reset all the hardware blocks that can act as DMA
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* masters on the bus.
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*/
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tegra_reset_all_dma_masters();
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/* clean up IRAM of any cruft */
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zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
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TEGRA_IRAM_A_SIZE);
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/* Copy the firmware to BPMP's internal RAM */
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(void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE,
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(const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES),
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plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES);
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/* Power on the BPMP and execute from IRAM base */
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tegra_fc_bpmp_on(TEGRA_IRAM_BASE);
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/* Wait until BPMP powers up */
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do {
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val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
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} while (val != SIGN_OF_LIFE);
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}
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/* enter system suspend */
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tegra_fc_soc_powerdn(mpidr);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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uint32_t cfg;
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uint32_t val, entrypoint = 0;
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uint64_t offset;
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/* platform parameter passed by the previous bootloader */
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if (plat_params->l2_ecc_parity_prot_dis != 1) {
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/* Enable ECC Parity Protection for Cortex-A57 CPUs */
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val = read_l2ctlr_el1();
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val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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}
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/*
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* Check if we are exiting from SOC_POWERDN.
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*/
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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PLAT_SYS_SUSPEND_STATE_ID) {
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/*
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* Security engine resume
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*/
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if (tegra_chipid_is_t210_b01()) {
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tegra_se_resume();
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}
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/*
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* Lock scratch registers which hold the CPU vectors
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*/
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tegra_pmc_lock_cpu_vectors();
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/*
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* Enable WRAP to INCR burst type conversions for
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* incoming requests on the AXI slave ports.
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*/
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val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG);
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val &= ~ENABLE_UNSUP_TX_ERRORS;
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val |= ENABLE_WRAP_TO_INCR_BURSTS;
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mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val);
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/*
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* Restore Boot and Power Management Processor (BPMP) reset
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* address and reset it, if it is supported by the platform.
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*/
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if (!tegra_bpmp_available) {
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tegra_fc_bpmp_off();
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} else {
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entrypoint = tegra_pmc_read_32(PMC_SCRATCH39);
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tegra_fc_bpmp_on(entrypoint);
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/* initialise the interface */
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tegra_bpmp_resume();
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}
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/* sc7entry-fw is part of TZDRAM area */
|
|
if (plat_params->sc7entry_fw_base != 0U) {
|
|
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
|
|
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
|
|
plat_params->tzdram_size + offset);
|
|
|
|
/* restrict PMC access to secure world */
|
|
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
|
|
val |= PMC_SECURITY_EN_BIT;
|
|
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check if we are exiting cluster idle state
|
|
*/
|
|
if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
|
|
PSTATE_ID_CLUSTER_IDLE) {
|
|
|
|
if (!tegra_bpmp_available) {
|
|
|
|
/* PWM un-tristate */
|
|
cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
|
|
if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
|
|
val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
|
|
val &= ~PINMUX_PWM_TRISTATE;
|
|
mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
|
|
|
|
/* make sure the setting took effect */
|
|
val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
|
|
assert((val & PINMUX_PWM_TRISTATE) == 0U);
|
|
}
|
|
|
|
/*
|
|
* Restore operation mode for the DFLL ring
|
|
* oscillator
|
|
*/
|
|
mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
|
|
ENABLE_CLOSED_LOOP);
|
|
|
|
/* release cluster idle lock */
|
|
tegra_fc_ccplex_pgexit_unlock();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
|
|
* used for power management and boot purposes. Inform the BPMP that
|
|
* we have completed the cluster power up.
|
|
*/
|
|
tegra_fc_lock_active_cluster();
|
|
|
|
/*
|
|
* Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
|
|
*/
|
|
if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
|
|
tegra_pmc_resume();
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
|
|
int tegra_soc_pwr_domain_on(u_register_t mpidr)
|
|
{
|
|
int cpu = mpidr & MPIDR_CPU_MASK;
|
|
uint32_t mask = CPU_CORE_RESET_MASK << cpu;
|
|
|
|
/* Deassert CPU reset signals */
|
|
mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
|
|
|
|
/* Turn on CPU using flow controller or PMC */
|
|
if (cpu_powergate_mask[cpu] == 0) {
|
|
tegra_pmc_cpu_on(cpu);
|
|
cpu_powergate_mask[cpu] = 1;
|
|
} else {
|
|
tegra_fc_cpu_on(cpu);
|
|
}
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
|
|
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
|
{
|
|
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
|
|
return PSCI_E_SUCCESS;
|
|
}
|
|
|
|
int tegra_soc_prepare_system_reset(void)
|
|
{
|
|
/*
|
|
* Set System Clock (SCLK) to POR default so that the clock source
|
|
* for the PMC APB clock would not be changed due to system reset.
|
|
*/
|
|
mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
|
|
SCLK_BURST_POLICY_DEFAULT);
|
|
mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
|
|
|
|
/* Wait 1 ms to make sure clock source/device logic is stabilized. */
|
|
mdelay(1);
|
|
|
|
return PSCI_E_SUCCESS;
|
|
}
|