343 lines
8.7 KiB
C
343 lines
8.7 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <bl31/interrupt_mgmt.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/cassert.h>
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#include <plat/common/platform.h>
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#ifdef IMAGE_BL31
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/*
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* The following platform GIC functions are weakly defined. They
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* provide typical implementations that may be re-used by multiple
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* platforms but may also be overridden by a platform if required.
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*/
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#pragma weak plat_ic_get_pending_interrupt_id
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#pragma weak plat_ic_get_pending_interrupt_type
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#pragma weak plat_ic_acknowledge_interrupt
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#pragma weak plat_ic_get_interrupt_type
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#pragma weak plat_ic_end_of_interrupt
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#pragma weak plat_interrupt_type_to_line
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#pragma weak plat_ic_get_running_priority
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#pragma weak plat_ic_is_spi
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#pragma weak plat_ic_is_ppi
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#pragma weak plat_ic_is_sgi
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#pragma weak plat_ic_get_interrupt_active
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#pragma weak plat_ic_enable_interrupt
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#pragma weak plat_ic_disable_interrupt
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#pragma weak plat_ic_set_interrupt_priority
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#pragma weak plat_ic_set_interrupt_type
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#pragma weak plat_ic_raise_el3_sgi
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#pragma weak plat_ic_set_spi_routing
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#pragma weak plat_ic_set_interrupt_pending
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#pragma weak plat_ic_clear_interrupt_pending
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CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) &&
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(INTR_TYPE_NS == INTR_GROUP1NS) &&
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(INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch);
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/*
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* This function returns the highest priority pending interrupt at
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* the Interrupt controller
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*/
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uint32_t plat_ic_get_pending_interrupt_id(void)
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{
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unsigned int irqnr;
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assert(IS_IN_EL3());
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irqnr = gicv3_get_pending_interrupt_id();
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return gicv3_is_intr_id_special_identifier(irqnr) ?
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INTR_ID_UNAVAILABLE : irqnr;
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}
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/*
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* This function returns the type of the highest priority pending interrupt
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* at the Interrupt controller. In the case of GICv3, the Highest Priority
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* Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine
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* the id of the pending interrupt. The type of interrupt depends upon the
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* id value as follows.
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* 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt
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* 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt.
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* 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt
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* type.
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* 4. All other interrupt id's are reported as EL3 interrupt.
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*/
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uint32_t plat_ic_get_pending_interrupt_type(void)
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{
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unsigned int irqnr;
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uint32_t type;
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assert(IS_IN_EL3());
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irqnr = gicv3_get_pending_interrupt_type();
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switch (irqnr) {
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case PENDING_G1S_INTID:
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type = INTR_TYPE_S_EL1;
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break;
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case PENDING_G1NS_INTID:
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type = INTR_TYPE_NS;
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break;
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case GIC_SPURIOUS_INTERRUPT:
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type = INTR_TYPE_INVAL;
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break;
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default:
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type = INTR_TYPE_EL3;
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break;
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}
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return type;
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}
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/*
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* This function returns the highest priority pending interrupt at
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* the Interrupt controller and indicates to the Interrupt controller
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* that the interrupt processing has started.
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*/
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uint32_t plat_ic_acknowledge_interrupt(void)
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{
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assert(IS_IN_EL3());
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return gicv3_acknowledge_interrupt();
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}
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/*
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* This function returns the type of the interrupt `id`, depending on how
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* the interrupt has been configured in the interrupt controller
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*/
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uint32_t plat_ic_get_interrupt_type(uint32_t id)
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{
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assert(IS_IN_EL3());
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return gicv3_get_interrupt_type(id, plat_my_core_pos());
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}
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/*
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* This functions is used to indicate to the interrupt controller that
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* the processing of the interrupt corresponding to the `id` has
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* finished.
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*/
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void plat_ic_end_of_interrupt(uint32_t id)
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{
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assert(IS_IN_EL3());
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gicv3_end_of_interrupt(id);
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}
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/*
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* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
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* The interrupt controller knows which pin/line it uses to signal a type of
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* interrupt. It lets the interrupt management framework determine for a type of
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* interrupt and security state, which line should be used in the SCR_EL3 to
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* control its routing to EL3. The interrupt line is represented as the bit
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* position of the IRQ or FIQ bit in the SCR_EL3.
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*/
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uint32_t plat_interrupt_type_to_line(uint32_t type,
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uint32_t security_state)
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{
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assert((type == INTR_TYPE_S_EL1) ||
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(type == INTR_TYPE_EL3) ||
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(type == INTR_TYPE_NS));
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assert(sec_state_is_valid(security_state));
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assert(IS_IN_EL3());
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switch (type) {
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case INTR_TYPE_S_EL1:
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/*
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* The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts
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* and as FIQ in the NS-EL0/1/2 contexts
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*/
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if (security_state == SECURE)
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return __builtin_ctz(SCR_IRQ_BIT);
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else
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return __builtin_ctz(SCR_FIQ_BIT);
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assert(0); /* Unreachable */
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case INTR_TYPE_NS:
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/*
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* The Non secure interrupts will be signaled as FIQ in S-EL0/1
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* contexts and as IRQ in the NS-EL0/1/2 contexts.
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*/
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if (security_state == SECURE)
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return __builtin_ctz(SCR_FIQ_BIT);
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else
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return __builtin_ctz(SCR_IRQ_BIT);
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assert(0); /* Unreachable */
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case INTR_TYPE_EL3:
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/*
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* The EL3 interrupts are signaled as FIQ in both S-EL0/1 and
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* NS-EL0/1/2 contexts
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*/
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return __builtin_ctz(SCR_FIQ_BIT);
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default:
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panic();
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}
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}
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unsigned int plat_ic_get_running_priority(void)
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{
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return gicv3_get_running_priority();
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}
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int plat_ic_is_spi(unsigned int id)
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{
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return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID);
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}
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int plat_ic_is_ppi(unsigned int id)
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{
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return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID);
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}
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int plat_ic_is_sgi(unsigned int id)
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{
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return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID);
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}
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unsigned int plat_ic_get_interrupt_active(unsigned int id)
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{
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return gicv3_get_interrupt_active(id, plat_my_core_pos());
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}
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void plat_ic_enable_interrupt(unsigned int id)
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{
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gicv3_enable_interrupt(id, plat_my_core_pos());
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}
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void plat_ic_disable_interrupt(unsigned int id)
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{
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gicv3_disable_interrupt(id, plat_my_core_pos());
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}
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void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
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{
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gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority);
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}
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int plat_ic_has_interrupt_type(unsigned int type)
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{
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assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) ||
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(type == INTR_TYPE_NS));
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return 1;
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}
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void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
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{
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gicv3_set_interrupt_type(id, plat_my_core_pos(), type);
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}
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void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
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{
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/* Target must be a valid MPIDR in the system */
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assert(plat_core_pos_by_mpidr(target) >= 0);
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/* Verify that this is a secure EL3 SGI */
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assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) ==
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INTR_TYPE_EL3);
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gicv3_raise_secure_g0_sgi((unsigned int)sgi_num, target);
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}
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void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
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u_register_t mpidr)
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{
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unsigned int irm = 0;
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switch (routing_mode) {
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case INTR_ROUTING_MODE_PE:
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assert(plat_core_pos_by_mpidr(mpidr) >= 0);
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irm = GICV3_IRM_PE;
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break;
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case INTR_ROUTING_MODE_ANY:
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irm = GICV3_IRM_ANY;
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break;
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default:
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assert(0); /* Unreachable */
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break;
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}
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gicv3_set_spi_routing(id, irm, mpidr);
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}
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void plat_ic_set_interrupt_pending(unsigned int id)
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{
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/* Disallow setting SGIs pending */
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assert(id >= MIN_PPI_ID);
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gicv3_set_interrupt_pending(id, plat_my_core_pos());
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}
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void plat_ic_clear_interrupt_pending(unsigned int id)
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{
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/* Disallow setting SGIs pending */
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assert(id >= MIN_PPI_ID);
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gicv3_clear_interrupt_pending(id, plat_my_core_pos());
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}
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unsigned int plat_ic_set_priority_mask(unsigned int mask)
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{
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return gicv3_set_pmr(mask);
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}
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unsigned int plat_ic_get_interrupt_id(unsigned int raw)
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{
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unsigned int id = raw & INT_ID_MASK;
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return gicv3_is_intr_id_special_identifier(id) ?
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INTR_ID_UNAVAILABLE : id;
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}
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#endif
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#ifdef IMAGE_BL32
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#pragma weak plat_ic_get_pending_interrupt_id
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#pragma weak plat_ic_acknowledge_interrupt
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#pragma weak plat_ic_end_of_interrupt
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/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
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#ifndef __aarch64__
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#define IS_IN_EL1() IS_IN_SECURE()
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#endif
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/*
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* This function returns the highest priority pending interrupt at
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* the Interrupt controller
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*/
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uint32_t plat_ic_get_pending_interrupt_id(void)
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{
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unsigned int irqnr;
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assert(IS_IN_EL1());
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irqnr = gicv3_get_pending_interrupt_id_sel1();
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return (irqnr == GIC_SPURIOUS_INTERRUPT) ?
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INTR_ID_UNAVAILABLE : irqnr;
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}
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/*
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* This function returns the highest priority pending interrupt at
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* the Interrupt controller and indicates to the Interrupt controller
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* that the interrupt processing has started.
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*/
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uint32_t plat_ic_acknowledge_interrupt(void)
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{
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assert(IS_IN_EL1());
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return gicv3_acknowledge_interrupt_sel1();
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}
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/*
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* This functions is used to indicate to the interrupt controller that
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* the processing of the interrupt corresponding to the `id` has
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* finished.
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*/
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void plat_ic_end_of_interrupt(uint32_t id)
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{
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assert(IS_IN_EL1());
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gicv3_end_of_interrupt_sel1(id);
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}
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#endif
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