327 lines
10 KiB
C
327 lines
10 KiB
C
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/extensions/amu.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include <smccc_helpers.h>
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/*******************************************************************************
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* Context management library initialisation routine. This library is used by
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* runtime services to share pointers to 'cpu_context' structures for the secure
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* and non-secure states. Management of the structures and their associated
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* memory is not done by the context management library e.g. the PSCI service
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* manages the cpu context used for entry from and exit to the non-secure state.
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* The Secure payload manages the context(s) corresponding to the secure state.
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* It also uses this library to get access to the non-secure
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* state cpu context pointers.
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******************************************************************************/
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void cm_init(void)
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{
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/*
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* The context management library has only global data to initialize, but
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* that will be done when the BSS is zeroed out
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*/
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}
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/*******************************************************************************
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* The following function initializes the cpu_context 'ctx' for
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* first use, and sets the initial entrypoint state as specified by the
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* entry_point_info structure.
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*
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* The security state to initialize is determined by the SECURE attribute
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* of the entry_point_info.
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*
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* The EE and ST attributes are used to configure the endianness and secure
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* timer availability for the new execution context.
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*
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* To prepare the register state for entry call cm_prepare_el3_exit() and
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* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
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* cm_e1_sysreg_context_restore().
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******************************************************************************/
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void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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{
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unsigned int security_state;
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uint32_t scr, sctlr;
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regs_t *reg_ctx;
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assert(ctx != NULL);
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security_state = GET_SECURITY_STATE(ep->h.attr);
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/* Clear any residual register values from the context */
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zeromem(ctx, sizeof(*ctx));
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reg_ctx = get_regs_ctx(ctx);
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/*
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* Base the context SCR on the current value, adjust for entry point
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* specific requirements
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*/
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scr = read_scr();
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scr &= ~(SCR_NS_BIT | SCR_HCE_BIT);
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if (security_state != SECURE)
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scr |= SCR_NS_BIT;
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if (security_state != SECURE) {
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/*
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* Set up SCTLR for the Non-secure context.
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*
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* SCTLR.EE: Endianness is taken from the entrypoint attributes.
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*
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* SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
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* required by PSCI specification)
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*
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* Set remaining SCTLR fields to their architecturally defined
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* values. Some fields reset to an IMPLEMENTATION DEFINED value:
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*
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* SCTLR.TE: Set to zero so that exceptions to an Exception
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* Level executing at PL1 are taken to A32 state.
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*
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* SCTLR.V: Set to zero to select the normal exception vectors
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* with base address held in VBAR.
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*/
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assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) ==
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(EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT));
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sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
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sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT));
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write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr);
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}
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/*
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* The target exception level is based on the spsr mode requested. If
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* execution is requested to hyp mode, HVC is enabled via SCR.HCE.
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*/
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if (GET_M32(ep->spsr) == MODE32_hyp)
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scr |= SCR_HCE_BIT;
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/*
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* Store the initialised values for SCTLR and SCR in the cpu_context.
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* The Hyp mode registers are not part of the saved context and are
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* set-up in cm_prepare_el3_exit().
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*/
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write_ctx_reg(reg_ctx, CTX_SCR, scr);
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write_ctx_reg(reg_ctx, CTX_LR, ep->pc);
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write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);
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/*
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* Store the r0-r3 value from the entrypoint into the context
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* Use memcpy as we are in control of the layout of the structures
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*/
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memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t));
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}
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/*******************************************************************************
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* Enable architecture extensions on first entry to Non-secure world.
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* When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
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* it is zero.
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******************************************************************************/
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static void enable_extensions_nonsecure(bool el2_unused)
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{
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#if IMAGE_BL32
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#if ENABLE_AMU
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amu_enable(el2_unused);
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#endif
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#endif
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}
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/*******************************************************************************
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* The following function initializes the cpu_context for a CPU specified by
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* its `cpu_idx` for first use, and sets the initial entrypoint state as
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* specified by the entry_point_info structure.
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******************************************************************************/
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void cm_init_context_by_index(unsigned int cpu_idx,
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const entry_point_info_t *ep)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
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cm_setup_context(ctx, ep);
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}
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/*******************************************************************************
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* The following function initializes the cpu_context for the current CPU
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* for first use, and sets the initial entrypoint state as specified by the
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* entry_point_info structure.
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******************************************************************************/
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void cm_init_my_context(const entry_point_info_t *ep)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
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cm_setup_context(ctx, ep);
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}
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/*******************************************************************************
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* Prepare the CPU system registers for first entry into secure or normal world
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*
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* If execution is requested to hyp mode, HSCTLR is initialized
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* If execution is requested to non-secure PL1, and the CPU supports
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* HYP mode then HYP mode is disabled by configuring all necessary HYP mode
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* registers.
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******************************************************************************/
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void cm_prepare_el3_exit(uint32_t security_state)
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{
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uint32_t hsctlr, scr;
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cpu_context_t *ctx = cm_get_context(security_state);
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bool el2_unused = false;
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assert(ctx != NULL);
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if (security_state == NON_SECURE) {
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scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR);
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if ((scr & SCR_HCE_BIT) != 0U) {
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/* Use SCTLR value to initialize HSCTLR */
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hsctlr = read_ctx_reg(get_regs_ctx(ctx),
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CTX_NS_SCTLR);
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hsctlr |= HSCTLR_RES1;
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/* Temporarily set the NS bit to access HSCTLR */
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write_scr(read_scr() | SCR_NS_BIT);
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/*
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* Make sure the write to SCR is complete so that
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* we can access HSCTLR
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*/
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isb();
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write_hsctlr(hsctlr);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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} else if ((read_id_pfr1() &
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(ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) != 0U) {
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el2_unused = true;
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/*
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* Set the NS bit to access NS copies of certain banked
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* registers
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*/
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write_scr(read_scr() | SCR_NS_BIT);
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isb();
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/*
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* Hyp / PL2 present but unused, need to disable safely.
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* HSCTLR can be ignored in this case.
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*
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* Set HCR to its architectural reset value so that
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* Non-secure operations do not trap to Hyp mode.
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*/
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write_hcr(HCR_RESET_VAL);
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/*
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* Set HCPTR to its architectural reset value so that
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* Non-secure access from EL1 or EL0 to trace and to
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* Advanced SIMD and floating point functionality does
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* not trap to Hyp mode.
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*/
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write_hcptr(HCPTR_RESET_VAL);
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/*
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* Initialise CNTHCTL. All fields are architecturally
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* UNKNOWN on reset and are set to zero except for
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* field(s) listed below.
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*
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* CNTHCTL.PL1PCEN: Disable traps to Hyp mode of
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* Non-secure EL0 and EL1 accessed to the physical
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* timer registers.
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*
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* CNTHCTL.PL1PCTEN: Disable traps to Hyp mode of
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* Non-secure EL0 and EL1 accessed to the physical
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* counter registers.
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*/
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write_cnthctl(CNTHCTL_RESET_VAL |
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PL1PCEN_BIT | PL1PCTEN_BIT);
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/*
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* Initialise CNTVOFF to zero as it resets to an
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* IMPLEMENTATION DEFINED value.
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*/
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write64_cntvoff(0);
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/*
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* Set VPIDR and VMPIDR to match MIDR_EL1 and MPIDR
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* respectively.
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*/
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write_vpidr(read_midr());
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write_vmpidr(read_mpidr());
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/*
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* Initialise VTTBR, setting all fields rather than
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* relying on the hw. Some fields are architecturally
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* UNKNOWN at reset.
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*
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* VTTBR.VMID: Set to zero which is the architecturally
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* defined reset value. Even though EL1&0 stage 2
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* address translation is disabled, cache maintenance
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* operations depend on the VMID.
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*
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* VTTBR.BADDR: Set to zero as EL1&0 stage 2 address
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* translation is disabled.
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*/
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write64_vttbr(VTTBR_RESET_VAL &
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~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
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| (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
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/*
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* Initialise HDCR, setting all the fields rather than
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* relying on hw.
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*
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* HDCR.HPMN: Set to value of PMCR.N which is the
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* architecturally-defined reset value.
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*
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* HDCR.HLP: Set to one so that event counter
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* overflow, that is recorded in PMOVSCLR[0-30],
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* occurs on the increment that changes
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* PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is
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* implemented. This bit is RES0 in versions of the
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* architecture earlier than ARMv8.5, setting it to 1
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* doesn't have any effect on them.
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* This bit is Reserved, UNK/SBZP in ARMv7.
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*
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* HDCR.HPME: Set to zero to disable EL2 Event
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* counters.
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*/
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#if (ARM_ARCH_MAJOR > 7)
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write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT |
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((read_pmcr() & PMCR_N_BITS) >>
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PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
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#else
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write_hdcr((HDCR_RESET_VAL |
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((read_pmcr() & PMCR_N_BITS) >>
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PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
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#endif
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/*
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* Set HSTR to its architectural reset value so that
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* access to system registers in the cproc=1111
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* encoding space do not trap to Hyp mode.
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*/
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write_hstr(HSTR_RESET_VAL);
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/*
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* Set CNTHP_CTL to its architectural reset value to
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* disable the EL2 physical timer and prevent timer
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* interrupts. Some fields are architecturally UNKNOWN
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* on reset and are set to zero.
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*/
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write_cnthp_ctl(CNTHP_CTL_RESET_VAL);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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}
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enable_extensions_nonsecure(el2_unused);
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}
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}
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