178 lines
5.5 KiB
C
178 lines
5.5 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef MARVELL_DEF_H
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#define MARVELL_DEF_H
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#include <platform_def.h>
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/common_def.h>
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/****************************************************************************
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* Definitions common to all MARVELL standard platforms
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****************************************************************************
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*/
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLAT_MARVELL_NORTHB_COUNT 1
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#define PLAT_MARVELL_CLUSTER_COUNT 1
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#define MARVELL_CACHE_WRITEBACK_SHIFT 6
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/*
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* Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
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* The power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
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#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
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#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in Marvell platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define MARVELL_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define MARVELL_LOCAL_STATE_RET 1
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/* Local power state for OFF/power-down.
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* Valid for CPU and cluster power domains
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*/
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#define MARVELL_LOCAL_STATE_OFF 2
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/* The first 4KB of Trusted SRAM are used as shared memory */
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#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
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#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
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#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
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/* The remaining Trusted SRAM is used to load the BL images */
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#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
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MARVELL_SHARED_RAM_SIZE)
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#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
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MARVELL_SHARED_RAM_SIZE)
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#define MARVELL_DRAM_BASE ULL(0x0)
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#define MARVELL_DRAM_SIZE ULL(0x20000000)
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#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
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MARVELL_DRAM_SIZE - 1)
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#define MARVELL_IRQ_SEC_PHY_TIMER 29
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#define MARVELL_IRQ_SEC_SGI_0 8
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#define MARVELL_IRQ_SEC_SGI_1 9
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#define MARVELL_IRQ_SEC_SGI_2 10
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#define MARVELL_IRQ_SEC_SGI_3 11
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#define MARVELL_IRQ_SEC_SGI_4 12
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#define MARVELL_IRQ_SEC_SGI_5 13
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#define MARVELL_IRQ_SEC_SGI_6 14
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#define MARVELL_IRQ_SEC_SGI_7 15
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#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
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MARVELL_SHARED_RAM_BASE, \
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MARVELL_SHARED_RAM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
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MARVELL_DRAM_BASE, \
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MARVELL_DRAM_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#if USE_COHERENT_MEM
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#define MARVELL_BL_REGIONS 3
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#else
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#define MARVELL_BL_REGIONS 2
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#endif
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#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \
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MARVELL_BL_REGIONS)
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#define MARVELL_CONSOLE_BAUDRATE 115200
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/****************************************************************************
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* Required platform porting definitions common to all MARVELL std. platforms
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****************************************************************************
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF
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#define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT)
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/*****************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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*****************************************************************************
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*/
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#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \
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+ PLAT_MARVELL_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM.
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*/
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#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE - \
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PLAT_MARVELL_MAX_BL1_RW_SIZE)
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#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
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/*****************************************************************************
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* BL2 specific defines.
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*****************************************************************************
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*/
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/*
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* Put BL2 just below BL31.
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*/
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#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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/*****************************************************************************
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* BL31 specific defines.
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*****************************************************************************
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*/
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/*
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* Put BL31 at the top of the Trusted SRAM.
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*/
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#define BL31_BASE (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE - \
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PLAT_MARVEL_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE)
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#endif /* MARVELL_DEF_H */
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