309 lines
7.7 KiB
ArmAsm
309 lines
7.7 KiB
ArmAsm
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert_macros.S>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <bl31/ea_handle.h>
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#include <context.h>
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#include <lib/extensions/ras_arch.h>
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#include <cpu_macros.S>
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#include <context.h>
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.globl handle_lower_el_ea_esb
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.globl enter_lower_el_sync_ea
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.globl enter_lower_el_async_ea
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/*
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* Function to delegate External Aborts synchronized by ESB instruction at EL3
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* vector entry. This function assumes GP registers x0-x29 have been saved, and
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* are available for use. It delegates the handling of the EA to platform
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* handler, and returns only upon successfully handling the EA; otherwise
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* panics. On return from this function, the original exception handler is
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* expected to resume.
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*/
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func handle_lower_el_ea_esb
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mov x0, #ERROR_EA_ESB
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mrs x1, DISR_EL1
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b ea_proceed
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endfunc handle_lower_el_ea_esb
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/*
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* This function forms the tail end of Synchronous Exception entry from lower
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* EL, and expects to handle Synchronous External Aborts from lower EL and CPU
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* Implementation Defined Exceptions. If any other kind of exception is detected,
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* then this function reports unhandled exception.
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*
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* Since it's part of exception vector, this function doesn't expect any GP
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* registers to have been saved. It delegates the handling of the EA to platform
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* handler, and upon successfully handling the EA, exits EL3; otherwise panics.
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*/
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func enter_lower_el_sync_ea
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching.
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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/* Check for I/D aborts from lower EL */
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cmp x30, #EC_IABORT_LOWER_EL
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b.eq 1f
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cmp x30, #EC_DABORT_LOWER_EL
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b.eq 1f
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/* Save GP registers */
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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/* Get the cpu_ops pointer */
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bl get_cpu_ops_ptr
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/* Get the cpu_ops exception handler */
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ldr x0, [x0, #CPU_E_HANDLER_FUNC]
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/*
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* If the reserved function pointer is NULL, this CPU does not have an
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* implementation defined exception handler function
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*/
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cbz x0, 2f
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mrs x1, esr_el3
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ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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blr x0
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b 2f
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1:
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/* Test for EA bit in the instruction syndrome */
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mrs x30, esr_el3
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tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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*/
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bl save_gp_pmcr_pauth_regs
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#if ENABLE_PAUTH
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/* Load and program APIAKey firmware key */
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bl pauth_load_bl31_apiakey
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#endif
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/* Setup exception class and syndrome arguments for platform handler */
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mov x0, #ERROR_EA_SYNC
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mrs x1, esr_el3
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adr x30, el3_exit
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b delegate_sync_ea
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2:
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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3:
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/* Synchronous exceptions other than the above are assumed to be EA */
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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no_ret report_unhandled_exception
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endfunc enter_lower_el_sync_ea
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/*
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* This function handles SErrors from lower ELs.
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*
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* Since it's part of exception vector, this function doesn't expect any GP
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* registers to have been saved. It delegates the handling of the EA to platform
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* handler, and upon successfully handling the EA, exits EL3; otherwise panics.
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*/
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func enter_lower_el_async_ea
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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*/
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bl save_gp_pmcr_pauth_regs
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#if ENABLE_PAUTH
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/* Load and program APIAKey firmware key */
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bl pauth_load_bl31_apiakey
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#endif
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/* Setup exception class and syndrome arguments for platform handler */
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mov x0, #ERROR_EA_ASYNC
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mrs x1, esr_el3
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adr x30, el3_exit
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b delegate_async_ea
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endfunc enter_lower_el_async_ea
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/*
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* Prelude for Synchronous External Abort handling. This function assumes that
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* all GP registers have been saved by the caller.
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*
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* x0: EA reason
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* x1: EA syndrome
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*/
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func delegate_sync_ea
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#if RAS_EXTENSION
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/*
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* Check for Uncontainable error type. If so, route to the platform
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* fatal error handler rather than the generic EA one.
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*/
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ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH
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cmp x2, #ERROR_STATUS_SET_UC
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b.ne 1f
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/* Check fault status code */
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ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
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cmp x3, #SYNC_EA_FSC
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b.ne 1f
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no_ret plat_handle_uncontainable_ea
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1:
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#endif
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b ea_proceed
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endfunc delegate_sync_ea
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/*
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* Prelude for Asynchronous External Abort handling. This function assumes that
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* all GP registers have been saved by the caller.
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*
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* x0: EA reason
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* x1: EA syndrome
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*/
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func delegate_async_ea
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#if RAS_EXTENSION
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/*
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* Check for Implementation Defined Syndrome. If so, skip checking
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* Uncontainable error type from the syndrome as the format is unknown.
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*/
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tbnz x1, #SERROR_IDS_BIT, 1f
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/*
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* Check for Uncontainable error type. If so, route to the platform
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* fatal error handler rather than the generic EA one.
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*/
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ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
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cmp x2, #ERROR_STATUS_UET_UC
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b.ne 1f
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/* Check DFSC for SError type */
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ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
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cmp x3, #DFSC_SERROR
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b.ne 1f
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no_ret plat_handle_uncontainable_ea
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1:
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#endif
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b ea_proceed
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endfunc delegate_async_ea
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/*
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* Delegate External Abort handling to platform's EA handler. This function
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* assumes that all GP registers have been saved by the caller.
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*
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* x0: EA reason
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* x1: EA syndrome
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*/
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func ea_proceed
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/*
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* If the ESR loaded earlier is not zero, we were processing an EA
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* already, and this is a double fault.
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*/
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ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
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cbz x5, 1f
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no_ret plat_handle_double_fault
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1:
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/* Save EL3 state */
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mrs x2, spsr_el3
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mrs x3, elr_el3
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stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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/*
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* Save ESR as handling might involve lower ELs, and returning back to
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* EL3 from there would trample the original ESR.
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*/
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mrs x4, scr_el3
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mrs x5, esr_el3
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stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
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/*
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* Setup rest of arguments, and call platform External Abort handler.
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*
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* x0: EA reason (already in place)
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* x1: Exception syndrome (already in place).
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* x2: Cookie (unused for now).
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* x3: Context pointer.
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* x4: Flags (security state from SCR for now).
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*/
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mov x2, xzr
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mov x3, sp
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ubfx x4, x4, #0, #1
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/* Switch to runtime stack */
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ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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msr spsel, #MODE_SP_EL0
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mov sp, x5
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mov x29, x30
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#if ENABLE_ASSERTIONS
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/* Stash the stack pointer */
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mov x28, sp
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#endif
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bl plat_ea_handler
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#if ENABLE_ASSERTIONS
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/*
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* Error handling flows might involve long jumps; so upon returning from
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* the platform error handler, validate that the we've completely
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* unwound the stack.
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*/
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mov x27, sp
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cmp x28, x27
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ASM_ASSERT(eq)
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#endif
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/* Make SP point to context */
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msr spsel, #MODE_SP_ELX
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/* Restore EL3 state and ESR */
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ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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msr spsr_el3, x1
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msr elr_el3, x2
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/* Restore ESR_EL3 and SCR_EL3 */
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ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
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msr scr_el3, x3
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msr esr_el3, x4
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#if ENABLE_ASSERTIONS
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cmp x4, xzr
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ASM_ASSERT(ne)
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#endif
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/* Clear ESR storage */
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
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ret x29
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endfunc ea_proceed
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