101 lines
1.8 KiB
C
101 lines
1.8 KiB
C
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Zynq UltraScale+ MPSoC IPI agent registers access management
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*/
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#include <errno.h>
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#include <string.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <ipi.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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/* Zynqmp ipi configuration table */
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const static struct ipi_config zynqmp_ipi_table[] = {
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/* APU IPI */
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{
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.ipi_bit_mask = 0x1,
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.ipi_reg_base = 0xFF300000,
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.secure_only = 0,
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},
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/* RPU0 IPI */
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{
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.ipi_bit_mask = 0x100,
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.ipi_reg_base = 0xFF310000,
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.secure_only = 0,
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},
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/* RPU1 IPI */
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{
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.ipi_bit_mask = 0x200,
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.ipi_reg_base = 0xFF320000,
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.secure_only = 0,
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},
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/* PMU0 IPI */
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{
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.ipi_bit_mask = 0x10000,
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.ipi_reg_base = 0xFF330000,
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.secure_only = IPI_SECURE_MASK,
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},
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/* PMU1 IPI */
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{
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.ipi_bit_mask = 0x20000,
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.ipi_reg_base = 0xFF331000,
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.secure_only = 0,
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},
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/* PMU2 IPI */
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{
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.ipi_bit_mask = 0x40000,
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.ipi_reg_base = 0xFF332000,
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.secure_only = IPI_SECURE_MASK,
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},
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/* PMU3 IPI */
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{
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.ipi_bit_mask = 0x80000,
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.ipi_reg_base = 0xFF333000,
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.secure_only = IPI_SECURE_MASK,
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},
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/* PL0 IPI */
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{
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.ipi_bit_mask = 0x1000000,
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.ipi_reg_base = 0xFF340000,
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.secure_only = 0,
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},
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/* PL1 IPI */
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{
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.ipi_bit_mask = 0x2000000,
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.ipi_reg_base = 0xFF350000,
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.secure_only = 0,
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},
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/* PL2 IPI */
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{
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.ipi_bit_mask = 0x4000000,
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.ipi_reg_base = 0xFF360000,
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.secure_only = 0,
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},
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/* PL3 IPI */
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{
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.ipi_bit_mask = 0x8000000,
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.ipi_reg_base = 0xFF370000,
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.secure_only = 0,
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},
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};
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/**
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* zynqmp_ipi_config_table_init() - Initialize ZynqMP IPI configuration data
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*
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*/
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void zynqmp_ipi_config_table_init(void)
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{
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ipi_config_table_init(zynqmp_ipi_table, ARRAY_SIZE(zynqmp_ipi_table));
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}
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