84 lines
1.7 KiB
C
84 lines
1.7 KiB
C
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* ZynqMP system level PM-API functions for pin control.
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*/
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#ifndef PM_API_IOCTL_H
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#define PM_API_IOCTL_H
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#include "pm_common.h"
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//ioctl id
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enum {
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IOCTL_GET_RPU_OPER_MODE,
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IOCTL_SET_RPU_OPER_MODE,
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IOCTL_RPU_BOOT_ADDR_CONFIG,
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IOCTL_TCM_COMB_CONFIG,
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IOCTL_SET_TAPDELAY_BYPASS,
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IOCTL_SET_SGMII_MODE,
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IOCTL_SD_DLL_RESET,
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IOCTL_SET_SD_TAPDELAY,
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/* Ioctl for clock driver */
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IOCTL_SET_PLL_FRAC_MODE,
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IOCTL_GET_PLL_FRAC_MODE,
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IOCTL_SET_PLL_FRAC_DATA,
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IOCTL_GET_PLL_FRAC_DATA,
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IOCTL_WRITE_GGS,
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IOCTL_READ_GGS,
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IOCTL_WRITE_PGGS,
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IOCTL_READ_PGGS,
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/* IOCTL for ULPI reset */
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IOCTL_ULPI_RESET,
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/* Set healthy bit value */
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IOCTL_SET_BOOT_HEALTH_STATUS,
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IOCTL_AFI,
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};
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//RPU operation mode
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#define PM_RPU_MODE_LOCKSTEP 0U
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#define PM_RPU_MODE_SPLIT 1U
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//RPU boot mem
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#define PM_RPU_BOOTMEM_LOVEC 0U
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#define PM_RPU_BOOTMEM_HIVEC 1U
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//RPU tcm mpde
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#define PM_RPU_TCM_SPLIT 0U
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#define PM_RPU_TCM_COMB 1U
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//tap delay signal type
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#define PM_TAPDELAY_NAND_DQS_IN 0U
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#define PM_TAPDELAY_NAND_DQS_OUT 1U
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#define PM_TAPDELAY_QSPI 2U
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#define PM_TAPDELAY_MAX 3U
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//tap delay bypass
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#define PM_TAPDELAY_BYPASS_DISABLE 0U
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#define PM_TAPDELAY_BYPASS_ENABLE 1U
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//sgmii mode
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#define PM_SGMII_DISABLE 0U
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#define PM_SGMII_ENABLE 1U
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enum tap_delay_type {
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PM_TAPDELAY_INPUT,
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PM_TAPDELAY_OUTPUT,
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};
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//dll reset type
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#define PM_DLL_RESET_ASSERT 0U
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#define PM_DLL_RESET_RELEASE 1U
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#define PM_DLL_RESET_PULSE 2U
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enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
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unsigned int ioctl_id,
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unsigned int arg1,
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unsigned int arg2,
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unsigned int *value);
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#endif /* PM_API_IOCTL_H */
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