318 lines
7.0 KiB
C
318 lines
7.0 KiB
C
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* ZynqMP system level PM-API functions for clock control.
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*/
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#ifndef PM_API_CLOCK_H
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#define PM_API_CLOCK_H
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#include <lib/utils_def.h>
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#include "pm_common.h"
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#define CLK_NAME_LEN U(15)
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#define MAX_PARENTS U(100)
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#define CLK_NA_PARENT -1
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#define CLK_DUMMY_PARENT -2
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/* Flags for parent id */
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#define PARENT_CLK_SELF U(0)
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#define PARENT_CLK_NODE1 U(1)
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#define PARENT_CLK_NODE2 U(2)
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#define PARENT_CLK_NODE3 U(3)
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#define PARENT_CLK_NODE4 U(4)
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#define PARENT_CLK_EXTERNAL U(5)
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#define PARENT_CLK_MIO0_MIO77 U(6)
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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/* unused */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
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#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
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/* parents need enable during gate/ungate, set rate and re-parent */
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#define CLK_OPS_PARENT_ENABLE BIT(12)
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#define CLK_FRAC BIT(13)
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
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#define CLK_DIVIDER_READ_ONLY BIT(5)
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#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
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#define END_OF_CLK "END_OF_CLK"
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//CLock Ids
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enum clock_id {
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CLK_IOPLL,
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CLK_RPLL,
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CLK_APLL,
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CLK_DPLL,
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CLK_VPLL,
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CLK_IOPLL_TO_FPD,
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CLK_RPLL_TO_FPD,
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CLK_APLL_TO_LPD,
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CLK_DPLL_TO_LPD,
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CLK_VPLL_TO_LPD,
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CLK_ACPU,
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CLK_ACPU_HALF,
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CLK_DBG_FPD,
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CLK_DBG_LPD,
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CLK_DBG_TRACE,
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CLK_DBG_TSTMP,
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CLK_DP_VIDEO_REF,
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CLK_DP_AUDIO_REF,
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CLK_DP_STC_REF,
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CLK_GDMA_REF,
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CLK_DPDMA_REF,
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CLK_DDR_REF,
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CLK_SATA_REF,
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CLK_PCIE_REF,
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CLK_GPU_REF,
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CLK_GPU_PP0_REF,
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CLK_GPU_PP1_REF,
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CLK_TOPSW_MAIN,
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CLK_TOPSW_LSBUS,
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CLK_GTGREF0_REF,
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CLK_LPD_SWITCH,
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CLK_LPD_LSBUS,
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CLK_USB0_BUS_REF,
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CLK_USB1_BUS_REF,
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CLK_USB3_DUAL_REF,
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CLK_USB0,
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CLK_USB1,
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CLK_CPU_R5,
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CLK_CPU_R5_CORE,
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CLK_CSU_SPB,
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CLK_CSU_PLL,
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CLK_PCAP,
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CLK_IOU_SWITCH,
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CLK_GEM_TSU_REF,
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CLK_GEM_TSU,
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CLK_GEM0_REF,
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CLK_GEM1_REF,
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CLK_GEM2_REF,
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CLK_GEM3_REF,
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CLK_GEM0_TX,
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CLK_GEM1_TX,
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CLK_GEM2_TX,
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CLK_GEM3_TX,
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CLK_QSPI_REF,
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CLK_SDIO0_REF,
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CLK_SDIO1_REF,
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CLK_UART0_REF,
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CLK_UART1_REF,
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CLK_SPI0_REF,
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CLK_SPI1_REF,
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CLK_NAND_REF,
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CLK_I2C0_REF,
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CLK_I2C1_REF,
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CLK_CAN0_REF,
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CLK_CAN1_REF,
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CLK_CAN0,
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CLK_CAN1,
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CLK_DLL_REF,
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CLK_ADMA_REF,
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CLK_TIMESTAMP_REF,
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CLK_AMS_REF,
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CLK_PL0_REF,
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CLK_PL1_REF,
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CLK_PL2_REF,
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CLK_PL3_REF,
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CLK_WDT,
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CLK_IOPLL_INT,
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CLK_IOPLL_PRE_SRC,
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CLK_IOPLL_HALF,
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CLK_IOPLL_INT_MUX,
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CLK_IOPLL_POST_SRC,
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CLK_RPLL_INT,
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CLK_RPLL_PRE_SRC,
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CLK_RPLL_HALF,
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CLK_RPLL_INT_MUX,
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CLK_RPLL_POST_SRC,
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CLK_APLL_INT,
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CLK_APLL_PRE_SRC,
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CLK_APLL_HALF,
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CLK_APLL_INT_MUX,
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CLK_APLL_POST_SRC,
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CLK_DPLL_INT,
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CLK_DPLL_PRE_SRC,
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CLK_DPLL_HALF,
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CLK_DPLL_INT_MUX,
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CLK_DPLL_POST_SRC,
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CLK_VPLL_INT,
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CLK_VPLL_PRE_SRC,
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CLK_VPLL_HALF,
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CLK_VPLL_INT_MUX,
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CLK_VPLL_POST_SRC,
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CLK_CAN0_MIO,
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CLK_CAN1_MIO,
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CLK_ACPU_FULL,
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END_OF_OUTPUT_CLKS,
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};
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#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
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//External clock ids
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enum {
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EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
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EXT_CLK_VIDEO,
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EXT_CLK_PSS_ALT_REF,
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EXT_CLK_AUX_REF,
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EXT_CLK_GT_CRX_REF,
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EXT_CLK_SWDT0,
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EXT_CLK_SWDT1,
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EXT_CLK_GEM0_EMIO,
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EXT_CLK_GEM1_EMIO,
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EXT_CLK_GEM2_EMIO,
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EXT_CLK_GEM3_EMIO,
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EXT_CLK_MIO50_OR_MIO51,
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EXT_CLK_MIO0,
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EXT_CLK_MIO1,
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EXT_CLK_MIO2,
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EXT_CLK_MIO3,
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EXT_CLK_MIO4,
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EXT_CLK_MIO5,
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EXT_CLK_MIO6,
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EXT_CLK_MIO7,
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EXT_CLK_MIO8,
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EXT_CLK_MIO9,
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EXT_CLK_MIO10,
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EXT_CLK_MIO11,
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EXT_CLK_MIO12,
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EXT_CLK_MIO13,
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EXT_CLK_MIO14,
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EXT_CLK_MIO15,
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EXT_CLK_MIO16,
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EXT_CLK_MIO17,
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EXT_CLK_MIO18,
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EXT_CLK_MIO19,
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EXT_CLK_MIO20,
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EXT_CLK_MIO21,
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EXT_CLK_MIO22,
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EXT_CLK_MIO23,
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EXT_CLK_MIO24,
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EXT_CLK_MIO25,
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EXT_CLK_MIO26,
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EXT_CLK_MIO27,
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EXT_CLK_MIO28,
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EXT_CLK_MIO29,
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EXT_CLK_MIO30,
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EXT_CLK_MIO31,
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EXT_CLK_MIO32,
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EXT_CLK_MIO33,
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EXT_CLK_MIO34,
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EXT_CLK_MIO35,
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EXT_CLK_MIO36,
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EXT_CLK_MIO37,
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EXT_CLK_MIO38,
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EXT_CLK_MIO39,
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EXT_CLK_MIO40,
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EXT_CLK_MIO41,
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EXT_CLK_MIO42,
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EXT_CLK_MIO43,
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EXT_CLK_MIO44,
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EXT_CLK_MIO45,
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EXT_CLK_MIO46,
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EXT_CLK_MIO47,
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EXT_CLK_MIO48,
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EXT_CLK_MIO49,
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EXT_CLK_MIO50,
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EXT_CLK_MIO51,
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EXT_CLK_MIO52,
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EXT_CLK_MIO53,
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EXT_CLK_MIO54,
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EXT_CLK_MIO55,
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EXT_CLK_MIO56,
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EXT_CLK_MIO57,
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EXT_CLK_MIO58,
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EXT_CLK_MIO59,
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EXT_CLK_MIO60,
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EXT_CLK_MIO61,
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EXT_CLK_MIO62,
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EXT_CLK_MIO63,
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EXT_CLK_MIO64,
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EXT_CLK_MIO65,
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EXT_CLK_MIO66,
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EXT_CLK_MIO67,
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EXT_CLK_MIO68,
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EXT_CLK_MIO69,
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EXT_CLK_MIO70,
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EXT_CLK_MIO71,
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EXT_CLK_MIO72,
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EXT_CLK_MIO73,
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EXT_CLK_MIO74,
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EXT_CLK_MIO75,
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EXT_CLK_MIO76,
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EXT_CLK_MIO77,
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END_OF_CLKS,
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};
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#define CLK_MAX (unsigned int)(END_OF_CLKS)
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//CLock types
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#define CLK_TYPE_OUTPUT 0U
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#define CLK_TYPE_EXTERNAL 1U
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//Topology types
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#define TYPE_INVALID 0U
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#define TYPE_MUX 1U
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#define TYPE_PLL 2U
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#define TYPE_FIXEDFACTOR 3U
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#define TYPE_DIV1 4U
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#define TYPE_DIV2 5U
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#define TYPE_GATE 6U
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struct pm_pll;
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struct pm_pll *pm_clock_get_pll(enum clock_id clock_id);
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struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
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uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id);
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enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
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enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
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enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
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unsigned int index,
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uint32_t *topology);
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enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
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uint32_t *mul,
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uint32_t *div);
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enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
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unsigned int index,
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uint32_t *parents);
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enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
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uint32_t *attr);
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enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
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enum pm_node_id *node_id);
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enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
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enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
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enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
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enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
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unsigned int *state);
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enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
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enum clock_id clock_id,
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unsigned int parent_index);
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enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
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enum clock_id clock_id,
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unsigned int *parent_index);
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enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
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unsigned int mode);
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enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
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unsigned int *mode);
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#endif /* PM_API_CLOCK_H */
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