744 lines
17 KiB
C
744 lines
17 KiB
C
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/*
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* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <common/debug.h>
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#include <drivers/st/stm32_gpio.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp1_shared_resources.h>
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static bool registering_locked;
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static int8_t gpioz_nbpin = -1;
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/*
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* Shared peripherals and resources.
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* Defines resource that may be non secure, secure or shared.
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* May be a device, a bus, a clock, a memory.
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* Shared peripherals and resources registration
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*
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* Each resource assignation is stored in a table. The state defaults
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* to SHRES_UNREGISTERED if the resource is not explicitly assigned.
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*
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* Each IO of the GPIOZ IO can be secure or non-secure.
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*/
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#define SHRES_NON_SECURE 2
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#define SHRES_SECURE 1
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#define SHRES_UNREGISTERED 0
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static uint8_t shres_state[STM32MP1_SHRES_COUNT];
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static const char *shres2str_id_tbl[STM32MP1_SHRES_COUNT] = {
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[STM32MP1_SHRES_GPIOZ(0)] = "GPIOZ0",
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[STM32MP1_SHRES_GPIOZ(1)] = "GPIOZ1",
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[STM32MP1_SHRES_GPIOZ(2)] = "GPIOZ2",
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[STM32MP1_SHRES_GPIOZ(3)] = "GPIOZ3",
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[STM32MP1_SHRES_GPIOZ(4)] = "GPIOZ4",
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[STM32MP1_SHRES_GPIOZ(5)] = "GPIOZ5",
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[STM32MP1_SHRES_GPIOZ(6)] = "GPIOZ6",
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[STM32MP1_SHRES_GPIOZ(7)] = "GPIOZ7",
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[STM32MP1_SHRES_IWDG1] = "IWDG1",
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[STM32MP1_SHRES_USART1] = "USART1",
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[STM32MP1_SHRES_SPI6] = "SPI6",
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[STM32MP1_SHRES_I2C4] = "I2C4",
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[STM32MP1_SHRES_RNG1] = "RNG1",
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[STM32MP1_SHRES_HASH1] = "HASH1",
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[STM32MP1_SHRES_CRYP1] = "CRYP1",
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[STM32MP1_SHRES_I2C6] = "I2C6",
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[STM32MP1_SHRES_RTC] = "RTC",
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[STM32MP1_SHRES_MCU] = "MCU",
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[STM32MP1_SHRES_MDMA] = "MDMA",
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[STM32MP1_SHRES_PLL3] = "PLL3",
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};
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static const char *shres2str_id(unsigned int id)
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{
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return shres2str_id_tbl[id];
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}
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static const char *shres2str_state_tbl[4] = {
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[SHRES_UNREGISTERED] = "unregistered",
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[SHRES_NON_SECURE] = "non-secure",
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[SHRES_SECURE] = "secure",
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};
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static const char *shres2str_state(unsigned int id)
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{
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return shres2str_state_tbl[id];
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}
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struct shres2decprot {
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unsigned int shres_id;
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unsigned int decprot_id;
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const char *decprot_str;
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};
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#define SHRES2DECPROT(shres, decprot, str) { \
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.shres_id = shres, \
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.decprot_id = decprot, \
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.decprot_str = str, \
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}
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#define SHRES_INVALID ~0U
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static const struct shres2decprot shres2decprot_tbl[] = {
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SHRES2DECPROT(STM32MP1_SHRES_IWDG1, STM32MP1_ETZPC_IWDG1_ID, "IWDG1"),
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SHRES2DECPROT(STM32MP1_SHRES_USART1, STM32MP1_ETZPC_USART1_ID, "UART1"),
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SHRES2DECPROT(STM32MP1_SHRES_SPI6, STM32MP1_ETZPC_SPI6_ID, "SPI6"),
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SHRES2DECPROT(STM32MP1_SHRES_I2C4, STM32MP1_ETZPC_I2C4_ID, "I2C4"),
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SHRES2DECPROT(STM32MP1_SHRES_RNG1, STM32MP1_ETZPC_RNG1_ID, "RNG1"),
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SHRES2DECPROT(STM32MP1_SHRES_HASH1, STM32MP1_ETZPC_HASH1_ID, "HASH1"),
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SHRES2DECPROT(STM32MP1_SHRES_CRYP1, STM32MP1_ETZPC_CRYP1_ID, "CRYP1"),
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SHRES2DECPROT(STM32MP1_SHRES_I2C6, STM32MP1_ETZPC_I2C6_ID, "I2C6"),
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/* Below are specific IDs without a 1-to-1 mapping to SHRES IDs */
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SHRES2DECPROT(SHRES_INVALID, STM32MP1_ETZPC_STGENC_ID, "STGEN"),
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SHRES2DECPROT(SHRES_INVALID, STM32MP1_ETZPC_BKPSRAM_ID, "BKPSRAM"),
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SHRES2DECPROT(SHRES_INVALID, STM32MP1_ETZPC_DDRCTRL_ID, "DDRCTRL"),
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SHRES2DECPROT(SHRES_INVALID, STM32MP1_ETZPC_DDRPHYC_ID, "DDRPHY"),
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};
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static unsigned int decprot2shres(unsigned int decprot_id)
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{
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uint32_t i;
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for (i = 0; i < ARRAY_SIZE(shres2decprot_tbl); i++) {
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if (shres2decprot_tbl[i].decprot_id == decprot_id) {
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return shres2decprot_tbl[i].shres_id;
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}
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}
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VERBOSE("No shared resource %u", decprot_id);
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return SHRES_INVALID;
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}
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static const char *decprot2str(unsigned int decprot_id)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(shres2decprot_tbl); i++) {
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if (shres2decprot_tbl[i].decprot_id == decprot_id) {
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return shres2decprot_tbl[i].decprot_str;
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}
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}
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ERROR("Invalid ID %u", decprot_id);
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panic();
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}
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static unsigned int get_gpioz_nbpin(void)
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{
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if (gpioz_nbpin < 0) {
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gpioz_nbpin = (int8_t)fdt_get_gpioz_nbpins_from_dt();
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assert((gpioz_nbpin == 0) ||
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(gpioz_nbpin == STM32MP_GPIOZ_PIN_MAX_COUNT));
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}
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return (unsigned int)gpioz_nbpin;
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}
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static void register_periph(unsigned int id, unsigned int state)
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{
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assert((id < STM32MP1_SHRES_COUNT) &&
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((state == SHRES_SECURE) || (state == SHRES_NON_SECURE)));
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if (registering_locked) {
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if (shres_state[id] == state) {
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return;
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}
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panic();
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}
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if ((shres_state[id] != SHRES_UNREGISTERED) &&
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(shres_state[id] != state)) {
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VERBOSE("Cannot change %s from %s to %s\n",
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shres2str_id(id),
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shres2str_state(shres_state[id]),
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shres2str_state(state));
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panic();
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}
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shres_state[id] = (uint8_t)state;
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if (shres_state[id] == SHRES_UNREGISTERED) {
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VERBOSE("Register %s as %s\n",
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shres2str_id(id), shres2str_state(state));
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}
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switch (id) {
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case STM32MP1_SHRES_GPIOZ(0) ... STM32MP1_SHRES_GPIOZ(7):
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if ((id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin()) {
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ERROR("Invalid GPIO pin %u, %u pin(s) available\n",
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id - STM32MP1_SHRES_GPIOZ(0),
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get_gpioz_nbpin());
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panic();
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}
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break;
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default:
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break;
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}
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/* Explore clock tree to lock dependencies */
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if (state == SHRES_SECURE) {
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switch (id) {
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case STM32MP1_SHRES_GPIOZ(0) ... STM32MP1_SHRES_GPIOZ(7):
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stm32mp1_register_clock_parents_secure(GPIOZ);
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break;
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case STM32MP1_SHRES_IWDG1:
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stm32mp1_register_clock_parents_secure(IWDG1);
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break;
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case STM32MP1_SHRES_USART1:
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stm32mp1_register_clock_parents_secure(USART1_K);
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break;
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case STM32MP1_SHRES_SPI6:
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stm32mp1_register_clock_parents_secure(SPI6_K);
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break;
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case STM32MP1_SHRES_I2C4:
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stm32mp1_register_clock_parents_secure(I2C4_K);
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break;
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case STM32MP1_SHRES_RNG1:
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stm32mp1_register_clock_parents_secure(RNG1_K);
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break;
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case STM32MP1_SHRES_HASH1:
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stm32mp1_register_clock_parents_secure(HASH1);
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break;
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case STM32MP1_SHRES_CRYP1:
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stm32mp1_register_clock_parents_secure(CRYP1);
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break;
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case STM32MP1_SHRES_I2C6:
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stm32mp1_register_clock_parents_secure(I2C6_K);
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break;
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case STM32MP1_SHRES_RTC:
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stm32mp1_register_clock_parents_secure(RTC);
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break;
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default:
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/* No expected resource dependency */
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break;
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}
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}
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}
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static bool stm32mp1_mckprot_resource(unsigned int id)
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{
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switch (id) {
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case STM32MP1_SHRES_MCU:
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case STM32MP1_SHRES_PLL3:
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return true;
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default:
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return false;
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}
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}
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/* Register resource by ID */
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void stm32mp_register_secure_periph(unsigned int id)
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{
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register_periph(id, SHRES_SECURE);
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}
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void stm32mp_register_non_secure_periph(unsigned int id)
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{
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register_periph(id, SHRES_NON_SECURE);
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}
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/* Register resource by IO memory base address */
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static void register_periph_iomem(uintptr_t base, unsigned int state)
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{
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unsigned int id;
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switch (base) {
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case IWDG1_BASE:
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id = STM32MP1_SHRES_IWDG1;
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break;
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case USART1_BASE:
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id = STM32MP1_SHRES_USART1;
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break;
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case SPI6_BASE:
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id = STM32MP1_SHRES_SPI6;
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break;
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case I2C4_BASE:
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id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_BASE:
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id = STM32MP1_SHRES_I2C6;
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break;
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case RTC_BASE:
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id = STM32MP1_SHRES_RTC;
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break;
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case RNG1_BASE:
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id = STM32MP1_SHRES_RNG1;
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break;
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case CRYP1_BASE:
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id = STM32MP1_SHRES_CRYP1;
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break;
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case HASH1_BASE:
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id = STM32MP1_SHRES_HASH1;
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break;
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case GPIOA_BASE:
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case GPIOB_BASE:
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case GPIOC_BASE:
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case GPIOD_BASE:
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case GPIOE_BASE:
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case GPIOF_BASE:
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case GPIOG_BASE:
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case GPIOH_BASE:
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case GPIOI_BASE:
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case GPIOJ_BASE:
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case GPIOK_BASE:
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case USART2_BASE:
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case USART3_BASE:
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case UART4_BASE:
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case UART5_BASE:
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case USART6_BASE:
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case UART7_BASE:
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case UART8_BASE:
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case IWDG2_BASE:
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/* Allow drivers to register some non-secure resources */
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VERBOSE("IO for non-secure resource 0x%x\n",
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(unsigned int)base);
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if (state != SHRES_NON_SECURE) {
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panic();
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}
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return;
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default:
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panic();
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break;
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}
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register_periph(id, state);
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}
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void stm32mp_register_secure_periph_iomem(uintptr_t base)
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{
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register_periph_iomem(base, SHRES_SECURE);
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}
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void stm32mp_register_non_secure_periph_iomem(uintptr_t base)
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{
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register_periph_iomem(base, SHRES_NON_SECURE);
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}
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/* Register GPIO resource */
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void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin)
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{
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switch (bank) {
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case GPIO_BANK_Z:
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register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_SECURE);
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break;
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default:
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ERROR("GPIO bank %u cannot be secured\n", bank);
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panic();
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}
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}
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void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin)
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{
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switch (bank) {
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case GPIO_BANK_Z:
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register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_NON_SECURE);
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break;
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default:
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break;
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}
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}
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void stm32mp1_register_etzpc_decprot(unsigned int id,
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|
|
enum etzpc_decprot_attributes attr)
|
||
|
|
{
|
||
|
|
unsigned int state = SHRES_SECURE;
|
||
|
|
unsigned int id_shres;
|
||
|
|
|
||
|
|
switch (attr) {
|
||
|
|
case TZPC_DECPROT_S_RW:
|
||
|
|
break;
|
||
|
|
case TZPC_DECPROT_NS_R_S_W:
|
||
|
|
case TZPC_DECPROT_MCU_ISOLATION:
|
||
|
|
case TZPC_DECPROT_NS_RW:
|
||
|
|
state = SHRES_NON_SECURE;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (id) {
|
||
|
|
case STM32MP1_ETZPC_STGENC_ID:
|
||
|
|
case STM32MP1_ETZPC_BKPSRAM_ID:
|
||
|
|
case STM32MP1_ETZPC_DDRCTRL_ID:
|
||
|
|
case STM32MP1_ETZPC_DDRPHYC_ID:
|
||
|
|
/* We assume these must always be assigned to secure world */
|
||
|
|
if (state != SHRES_SECURE) {
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
id_shres = decprot2shres(id);
|
||
|
|
if (id_shres == SHRES_INVALID) {
|
||
|
|
if (state == SHRES_SECURE) {
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
register_periph(id_shres, state);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get resource state: these accesses lock the registering support */
|
||
|
|
static void lock_registering(void)
|
||
|
|
{
|
||
|
|
registering_locked = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool stm32mp1_periph_is_non_secure(unsigned long id)
|
||
|
|
{
|
||
|
|
lock_registering();
|
||
|
|
|
||
|
|
/* Resource not registered are assumed non-secure */
|
||
|
|
return (shres_state[id] == SHRES_NON_SECURE) ||
|
||
|
|
(shres_state[id] == SHRES_UNREGISTERED);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool stm32mp1_periph_is_secure(unsigned long id)
|
||
|
|
{
|
||
|
|
lock_registering();
|
||
|
|
|
||
|
|
return shres_state[id] == SHRES_SECURE;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool stm32mp_gpio_bank_is_shared(unsigned int bank)
|
||
|
|
{
|
||
|
|
unsigned int non_secure = 0;
|
||
|
|
unsigned int i;
|
||
|
|
|
||
|
|
lock_registering();
|
||
|
|
|
||
|
|
if (bank != GPIO_BANK_Z) {
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0U; i < get_gpioz_nbpin(); i++) {
|
||
|
|
if (!stm32mp1_periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) {
|
||
|
|
non_secure++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return (non_secure != 0) && (non_secure < get_gpioz_nbpin());
|
||
|
|
}
|
||
|
|
|
||
|
|
bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
|
||
|
|
{
|
||
|
|
unsigned int non_secure = 0;
|
||
|
|
unsigned int i;
|
||
|
|
|
||
|
|
lock_registering();
|
||
|
|
|
||
|
|
if (bank != GPIO_BANK_Z) {
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0U; i < get_gpioz_nbpin(); i++) {
|
||
|
|
if (!stm32mp1_periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) {
|
||
|
|
non_secure++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return non_secure == get_gpioz_nbpin();
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool stm32mp_gpio_bank_is_secure(unsigned int bank)
|
||
|
|
{
|
||
|
|
unsigned int secure = 0;
|
||
|
|
unsigned int i;
|
||
|
|
|
||
|
|
lock_registering();
|
||
|
|
|
||
|
|
if (bank != GPIO_BANK_Z) {
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0U; i < get_gpioz_nbpin(); i++) {
|
||
|
|
if (stm32mp1_periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) {
|
||
|
|
secure++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return secure == get_gpioz_nbpin();
|
||
|
|
}
|
||
|
|
|
||
|
|
CASSERT((CK_HSE == 0) &&
|
||
|
|
((CK_HSE + 1) == CK_CSI) &&
|
||
|
|
((CK_HSE + 2) == CK_LSI) &&
|
||
|
|
((CK_HSE + 3) == CK_LSE) &&
|
||
|
|
((CK_HSE + 4) == CK_HSI) &&
|
||
|
|
((CK_HSE + 5) == CK_HSE_DIV2) &&
|
||
|
|
((PLL1_P + 1) == PLL1_Q) &&
|
||
|
|
((PLL1_P + 2) == PLL1_R) &&
|
||
|
|
((PLL1_P + 3) == PLL2_P) &&
|
||
|
|
((PLL1_P + 4) == PLL2_Q) &&
|
||
|
|
((PLL1_P + 5) == PLL2_R) &&
|
||
|
|
((PLL1_P + 6) == PLL3_P) &&
|
||
|
|
((PLL1_P + 7) == PLL3_Q) &&
|
||
|
|
((PLL1_P + 8) == PLL3_R),
|
||
|
|
assert_clock_id_not_as_expected);
|
||
|
|
|
||
|
|
bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
|
||
|
|
{
|
||
|
|
enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
|
||
|
|
|
||
|
|
/* Oscillators and PLLs are visible from non-secure world */
|
||
|
|
if ((clock_id <= CK_HSE_DIV2) ||
|
||
|
|
((clock_id >= PLL1_P) && (clock_id <= PLL3_R))) {
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (clock_id) {
|
||
|
|
case BSEC:
|
||
|
|
case CK_AXI:
|
||
|
|
case CK_MPU:
|
||
|
|
case RTCAPB:
|
||
|
|
return true;
|
||
|
|
case GPIOZ:
|
||
|
|
return !stm32mp_gpio_bank_is_secure(GPIO_BANK_Z);
|
||
|
|
case SPI6_K:
|
||
|
|
shres_id = STM32MP1_SHRES_SPI6;
|
||
|
|
break;
|
||
|
|
case I2C4_K:
|
||
|
|
shres_id = STM32MP1_SHRES_I2C4;
|
||
|
|
break;
|
||
|
|
case I2C6_K:
|
||
|
|
shres_id = STM32MP1_SHRES_I2C6;
|
||
|
|
break;
|
||
|
|
case USART1_K:
|
||
|
|
shres_id = STM32MP1_SHRES_USART1;
|
||
|
|
break;
|
||
|
|
case IWDG1:
|
||
|
|
shres_id = STM32MP1_SHRES_IWDG1;
|
||
|
|
break;
|
||
|
|
case CRYP1:
|
||
|
|
shres_id = STM32MP1_SHRES_CRYP1;
|
||
|
|
break;
|
||
|
|
case HASH1:
|
||
|
|
shres_id = STM32MP1_SHRES_HASH1;
|
||
|
|
break;
|
||
|
|
case RNG1_K:
|
||
|
|
shres_id = STM32MP1_SHRES_RNG1;
|
||
|
|
break;
|
||
|
|
case RTC:
|
||
|
|
shres_id = STM32MP1_SHRES_RTC;
|
||
|
|
break;
|
||
|
|
case CK_MCU:
|
||
|
|
shres_id = STM32MP1_SHRES_MCU;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return !stm32mp1_periph_is_secure(shres_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
|
||
|
|
{
|
||
|
|
enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
|
||
|
|
|
||
|
|
switch (reset_id) {
|
||
|
|
case GPIOZ_R:
|
||
|
|
return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z);
|
||
|
|
case SPI6_R:
|
||
|
|
shres_id = STM32MP1_SHRES_SPI6;
|
||
|
|
break;
|
||
|
|
case I2C4_R:
|
||
|
|
shres_id = STM32MP1_SHRES_I2C4;
|
||
|
|
break;
|
||
|
|
case I2C6_R:
|
||
|
|
shres_id = STM32MP1_SHRES_I2C6;
|
||
|
|
break;
|
||
|
|
case USART1_R:
|
||
|
|
shres_id = STM32MP1_SHRES_USART1;
|
||
|
|
break;
|
||
|
|
case CRYP1_R:
|
||
|
|
shres_id = STM32MP1_SHRES_CRYP1;
|
||
|
|
break;
|
||
|
|
case HASH1_R:
|
||
|
|
shres_id = STM32MP1_SHRES_HASH1;
|
||
|
|
break;
|
||
|
|
case RNG1_R:
|
||
|
|
shres_id = STM32MP1_SHRES_RNG1;
|
||
|
|
break;
|
||
|
|
case MDMA_R:
|
||
|
|
shres_id = STM32MP1_SHRES_MDMA;
|
||
|
|
break;
|
||
|
|
case MCU_R:
|
||
|
|
shres_id = STM32MP1_SHRES_MCU;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return !stm32mp1_periph_is_secure(shres_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ETZPC configuration at drivers initialization completion */
|
||
|
|
static enum etzpc_decprot_attributes decprot_periph_attr(unsigned int id)
|
||
|
|
{
|
||
|
|
switch (id) {
|
||
|
|
case STM32MP1_SHRES_GPIOZ(0) ... STM32MP1_SHRES_GPIOZ(7):
|
||
|
|
assert((id - STM32MP1_SHRES_GPIOZ(0)) < get_gpioz_nbpin());
|
||
|
|
return TZPC_DECPROT_NS_RW;
|
||
|
|
default:
|
||
|
|
if (!stm32mp1_periph_is_secure(id)) {
|
||
|
|
return TZPC_DECPROT_NS_RW;
|
||
|
|
}
|
||
|
|
|
||
|
|
return TZPC_DECPROT_S_RW;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool check_decprot(unsigned int id, enum etzpc_decprot_attributes exp)
|
||
|
|
{
|
||
|
|
enum etzpc_decprot_attributes cur = etzpc_get_decprot(id);
|
||
|
|
|
||
|
|
if (cur == exp) {
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (exp) {
|
||
|
|
case TZPC_DECPROT_NS_RW:
|
||
|
|
if (cur == TZPC_DECPROT_S_RW) {
|
||
|
|
INFO("ETZPC: %s (%d) could be non secure\n",
|
||
|
|
decprot2str(id), id);
|
||
|
|
}
|
||
|
|
return true;
|
||
|
|
|
||
|
|
case TZPC_DECPROT_S_RW:
|
||
|
|
ERROR("ETZPC: %s (%d) expected secure but DECPROT = %d\n",
|
||
|
|
decprot2str(id), id, cur);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case TZPC_DECPROT_NS_R_S_W:
|
||
|
|
case TZPC_DECPROT_MCU_ISOLATION:
|
||
|
|
default:
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void check_etzpc_secure_configuration(void)
|
||
|
|
{
|
||
|
|
bool error = false;
|
||
|
|
|
||
|
|
assert(registering_locked);
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_STGENC_ID, TZPC_DECPROT_S_RW);
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_BKPSRAM_ID, TZPC_DECPROT_S_RW);
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_USART1_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_USART1));
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_SPI6_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_SPI6));
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_I2C4_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_I2C4));
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_RNG1_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_RNG1));
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_HASH1_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_HASH1));
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_CRYP1_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_CRYP1));
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_DDRCTRL_ID, TZPC_DECPROT_S_RW);
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_DDRPHYC_ID, TZPC_DECPROT_S_RW);
|
||
|
|
|
||
|
|
error |= !check_decprot(STM32MP1_ETZPC_I2C6_ID,
|
||
|
|
decprot_periph_attr(STM32MP1_SHRES_I2C6));
|
||
|
|
|
||
|
|
if (error) {
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void check_rcc_secure_configuration(void)
|
||
|
|
{
|
||
|
|
uint32_t n;
|
||
|
|
uint32_t error = 0;
|
||
|
|
bool mckprot = stm32mp1_rcc_is_mckprot();
|
||
|
|
bool secure = stm32mp1_rcc_is_secure();
|
||
|
|
|
||
|
|
for (n = 0; n < ARRAY_SIZE(shres_state); n++) {
|
||
|
|
if (shres_state[n] == SHRES_SECURE) {
|
||
|
|
if ((stm32mp1_mckprot_resource(n) && (!mckprot)) ||
|
||
|
|
!secure) {
|
||
|
|
ERROR("RCC %s MCKPROT %s and %s (%u) secure\n",
|
||
|
|
secure ? "secure" : "non secure",
|
||
|
|
mckprot ? "set" : "not set",
|
||
|
|
shres2str_id(n), n);
|
||
|
|
error++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (error != 0U) {
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void check_gpio_secure_configuration(void)
|
||
|
|
{
|
||
|
|
uint32_t pin;
|
||
|
|
|
||
|
|
for (pin = 0U; pin < get_gpioz_nbpin(); pin++) {
|
||
|
|
unsigned int id = STM32MP1_SHRES_GPIOZ(pin);
|
||
|
|
bool secure = stm32mp1_periph_is_secure(id);
|
||
|
|
|
||
|
|
set_gpio_secure_cfg(GPIO_BANK_Z, pin, secure);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void stm32mp_lock_periph_registering(void)
|
||
|
|
{
|
||
|
|
uint32_t __unused id;
|
||
|
|
|
||
|
|
registering_locked = true;
|
||
|
|
|
||
|
|
for (id = 0; id < STM32MP1_SHRES_COUNT; id++) {
|
||
|
|
uint8_t state = shres_state[id];
|
||
|
|
|
||
|
|
assert((state == SHRES_SECURE) ||
|
||
|
|
(state == SHRES_NON_SECURE) ||
|
||
|
|
(state == SHRES_UNREGISTERED));
|
||
|
|
|
||
|
|
if (state == SHRES_SECURE) {
|
||
|
|
INFO("stm32mp %s (%u): %s\n",
|
||
|
|
shres2str_id(id), id,
|
||
|
|
state == SHRES_SECURE ? "Secure" :
|
||
|
|
state == SHRES_NON_SECURE ? "Non-secure" :
|
||
|
|
state == SHRES_UNREGISTERED ? "Unregistered" :
|
||
|
|
"<Invalid>");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
stm32mp1_dump_clocks_state();
|
||
|
|
|
||
|
|
check_rcc_secure_configuration();
|
||
|
|
check_etzpc_secure_configuration();
|
||
|
|
check_gpio_secure_configuration();
|
||
|
|
}
|