100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
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/*
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* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* This function flushes the data structures so that they are visible
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* in memory for the next BL image.
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******************************************************************************/
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void plat_flush_next_bl_params(void)
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{
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flush_bl_params_desc();
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}
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#ifdef AARCH32_SP_OPTEE
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static bool addr_inside_backupsram(uintptr_t addr)
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{
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return (addr >= STM32MP_BACKUP_RAM_BASE) &&
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(addr < (STM32MP_BACKUP_RAM_BASE + STM32MP_BACKUP_RAM_SIZE));
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}
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#endif
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/*******************************************************************************
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* This function returns the list of loadable images.
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******************************************************************************/
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bl_load_info_t *plat_get_bl_image_load_info(void)
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{
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp_get_boot_ctx_address();
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#ifdef AARCH32_SP_OPTEE
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bl_mem_params_node_t *bl32 = get_bl_mem_params_node(BL32_IMAGE_ID);
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#endif
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bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
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uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
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uint32_t bkpr_core1_addr =
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tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
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uintptr_t pwr_base = stm32mp_pwr_base();
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/*
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* If going back from CSTANDBY / STANDBY and DDR was in Self-Refresh,
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* BL33 must not be loaded as it would overwrite the code already
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* in DDR. For this, the BL33 part of the bl_mem_params_desc_ptr
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* struct should be modified to skip its loading
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*/
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if (((boot_context->boot_action ==
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BOOT_API_CTX_BOOT_ACTION_WAKEUP_CSTANDBY) ||
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(boot_context->boot_action ==
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BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY)) &&
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((mmio_read_32(pwr_base + PWR_CR3) & PWR_CR3_DDRSREN) != 0U) &&
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((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U)) {
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stm32mp_clk_enable(RTCAPB);
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if (mmio_read_32(bkpr_core1_addr) != 0U) {
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bl33->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
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#ifdef AARCH32_SP_OPTEE
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bl32->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
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bl32->ep_info.pc = stm32_pm_get_optee_ep();
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if (addr_inside_backupsram(bl32->ep_info.pc)) {
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stm32mp_clk_enable(BKPSRAM);
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}
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#else
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/*
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* Set ep_info PC to 0, to inform BL32 it is a reset
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* after STANDBY
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*/
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bl33->ep_info.pc = 0;
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#endif
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}
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stm32mp_clk_disable(RTCAPB);
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}
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/* Max size is non-secure DDR end address minus image_base */
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bl33->image_info.image_max_size = STM32MP_DDR_BASE +
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dt_get_ddr_size() -
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STM32MP_DDR_S_SIZE -
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STM32MP_DDR_SHMEM_SIZE -
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bl33->image_info.image_base;
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return get_bl_load_info_from_mem_params_desc();
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}
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/*******************************************************************************
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* This function returns the list of executable images.
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******************************************************************************/
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bl_params_t *plat_get_next_bl_params(void)
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{
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return get_next_bl_params_from_mem_params_desc();
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}
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