214 lines
7.2 KiB
C
214 lines
7.2 KiB
C
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include "../stm32mp1_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL32)
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#define PLATFORM_STACK_SIZE 0x600
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#else
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#define PLATFORM_STACK_SIZE 0xC00
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#endif
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#ifdef AARCH32_SP_OPTEE
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#define OPTEE_HEADER_IMAGE_NAME "teeh"
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#define OPTEE_PAGED_IMAGE_NAME "teed"
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#define OPTEE_PAGER_IMAGE_NAME "teex"
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#define OPTEE_HEADER_BINARY_TYPE U(0x20)
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#define OPTEE_PAGER_BINARY_TYPE U(0x21)
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#define OPTEE_PAGED_BINARY_TYPE U(0x22)
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#endif
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/* SSBL = second stage boot loader */
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#define BL33_IMAGE_NAME "ssbl"
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#define BL33_BINARY_TYPE U(0x0)
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#define STM32MP_PRIMARY_CPU U(0x0)
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#define STM32MP_SECONDARY_CPU U(0x1)
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#define PLATFORM_CLUSTER_COUNT ULL(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
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#define MAX_IO_DEVICES U(4)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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#define MAX_IO_MTD_DEVICES U(1)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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/*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE STM32MP_BL2_BASE
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#define BL2_LIMIT (STM32MP_BL2_BASE + \
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STM32MP_BL2_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#ifndef AARCH32_SP_OPTEE
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#define BL32_BASE STM32MP_BL32_BASE
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#define BL32_LIMIT (STM32MP_BL32_BASE + \
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STM32MP_BL32_SIZE)
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#endif
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/*******************************************************************************
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* BL33 specific defines.
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******************************************************************************/
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#define BL33_BASE STM32MP_BL33_BASE
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/*
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* Load address of BL33 for this platform port
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*/
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#define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE
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/* need by flash programmer */
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#define FLASHLAYOUT_BASE STM32MP_DDR_BASE
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#define FLASHLAYOUT_LIMIT STM32MP_BL33_BASE
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/*******************************************************************************
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* DTB specific defines.
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******************************************************************************/
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#define DTB_BASE STM32MP_DTB_BASE
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#define DTB_LIMIT (STM32MP_DTB_BASE + \
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STM32MP_DTB_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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/*
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* Secure Interrupt: based on the standard ARM mapping
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*/
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#define ARM_IRQ_SEC_PHY_TIMER U(29)
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#define ARM_IRQ_NON_SEC_SGI_0 U(0)
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#define ARM_IRQ_SEC_SGI_0 U(8)
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#define ARM_IRQ_SEC_SGI_1 U(9)
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#define ARM_IRQ_SEC_SGI_2 U(10)
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#define ARM_IRQ_SEC_SGI_3 U(11)
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#define ARM_IRQ_SEC_SGI_4 U(12)
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#define ARM_IRQ_SEC_SGI_5 U(13)
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#define ARM_IRQ_SEC_SGI_6 U(14)
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#define ARM_IRQ_SEC_SGI_7 U(15)
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/* Platform IRQ Priority */
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#define STM32MP1_IRQ_RCC_SEC_PRIO U(0x6)
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#define STM32MP_IRQ_SEC_SPI_PRIO U(0x10)
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#define STM32MP1_IRQ_TZC400 U(36)
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#define STM32MP1_IRQ_MCU_SEV U(176)
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#define STM32MP1_IRQ_RCC_WAKEUP U(177)
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#define STM32MP1_IRQ_IWDG1 U(182)
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#define STM32MP1_IRQ_IWDG2 U(183)
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#define STM32MP1_IRQ_TAMPSERRS U(229)
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#define STM32MP1_IRQ_AXIERRIRQ U(244)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE)
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#define PLATFORM_G0_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
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GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE)
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/*
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* Power
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*/
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#define PLAT_MAX_PWR_LVL U(1)
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/* Local power state for power domains in Run state. */
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#define ARM_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define ARM_LOCAL_STATE_RET U(1)
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/* Local power state for power-down. Valid for CPU and cluster power domains */
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#define ARM_LOCAL_STATE_OFF U(2)
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/*
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* This macro defines the deepest retention state possible.
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* A higher state id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
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/*******************************************************************************
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* Size of the per-cpu data in bytes that should be reserved in the generic
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* per-cpu data structure for the FVP port.
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******************************************************************************/
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#define PLAT_PCPU_DATA_SIZE 2
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#endif /* PLATFORM_DEF_H */
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