138 lines
3.7 KiB
C
138 lines
3.7 KiB
C
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include "rpi_hw.h"
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
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#define PLATFORM_STACK_SIZE ULL(0x1000)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define RPI4_PRIMARY_CPU U(0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET U(1)
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF U(2)
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH U(4)
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#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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/*
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* I/O registers.
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*/
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#define DEVICE0_BASE RPI_IO_BASE
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#define DEVICE0_SIZE RPI_IO_SIZE
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/*
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* Mailbox to control the secondary cores. All secondary cores are held in a
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* wait loop in cold boot. To release them perform the following steps (plus
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* any additional barriers that may be needed):
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*
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* uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
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* *entrypoint = ADDRESS_TO_JUMP_TO;
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*
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* uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
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* mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
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*
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* sev();
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*/
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/* The secure entry point to be used on warm reset by all CPUs. */
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#define PLAT_RPI3_TM_ENTRYPOINT 0x100
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#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
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/* Hold entries for each CPU. */
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#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \
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PLAT_RPI3_TM_ENTRYPOINT_SIZE)
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#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
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#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
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PLATFORM_CORE_COUNT)
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#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
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PLAT_RPI3_TM_HOLD_SIZE)
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#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
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#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
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/*
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* BL31 specific defines.
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*
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* Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL31 debug size plus a little space for growth.
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*/
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#define PLAT_MAX_BL31_SIZE ULL(0x80000)
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#define BL31_BASE ULL(0x1000)
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#define BL31_LIMIT ULL(0x80000)
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#define BL31_PROGBITS_LIMIT ULL(0x80000)
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#define SEC_SRAM_ID 0
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#define SEC_DRAM_ID 1
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/*
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* Other memory-related defines.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 4
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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/*
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* Serial-related constants.
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*/
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#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
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#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ULL(54000000)
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#endif /* PLATFORM_DEF_H */
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