244 lines
7.3 KiB
C
244 lines
7.3 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <tbbr_img_def.h>
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT)
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#define QEMU_PRIMARY_CPU 0
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET 1
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF 2
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH 4
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#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*
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* Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
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* and secure DRAM.
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*/
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#define SEC_ROM_BASE 0x00000000
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#define SEC_ROM_SIZE 0x00020000
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#define NS_DRAM0_BASE 0x10000000000ULL
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#define NS_DRAM0_SIZE 0x00020000000
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#define SEC_SRAM_BASE 0x20000000
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#define SEC_SRAM_SIZE 0x20000000
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/*
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* RAD just placeholders, need to be chosen after finalizing mem map
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*/
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#define SEC_DRAM_BASE 0x1000
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#define SEC_DRAM_SIZE 0x1000
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/* Load pageable part of OP-TEE 2MB above secure DRAM base */
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#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000)
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#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
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/*
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* ARM-TF lives in SRAM, partition it here
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*/
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#define SHARED_RAM_BASE SEC_SRAM_BASE
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#define SHARED_RAM_SIZE 0x00001000
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#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
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#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE)
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#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
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#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_QEMU_HOLD_ENTRY_SIZE)
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#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3
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#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT)
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#define PLAT_QEMU_HOLD_STATE_WAIT 0
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#define PLAT_QEMU_HOLD_STATE_GO 1
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#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
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#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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/*
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* BL1 specific defines.
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*
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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* Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#define BL1_RO_BASE SEC_ROM_BASE
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#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
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#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000)
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#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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/*
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* BL2 specific defines.
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*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE (BL31_BASE - 0x1D000)
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#define BL2_LIMIT BL31_BASE
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/*
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* BL3-1 specific defines.
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*
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (BL31_LIMIT - 0x20000)
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#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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/*
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* BL3-2 specific defines.
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*
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* BL3-2 can execute from Secure SRAM, or Secure DRAM.
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*/
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#define BL32_SRAM_BASE BL_RAM_BASE
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#define BL32_SRAM_LIMIT BL31_BASE
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#define BL32_DRAM_BASE SEC_DRAM_BASE
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#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
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#define BL32_MEM_BASE BL_RAM_BASE
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#define BL32_MEM_SIZE BL_RAM_SIZE
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000)
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#define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42)
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#define MAX_MMAP_REGIONS 11
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#define MAX_XLAT_TABLES 10
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/*
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* PL011 related constants
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*/
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#define UART0_BASE 0x60000000
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#define UART1_BASE 0x60030000
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#define UART0_CLK_IN_HZ 1
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#define UART1_CLK_IN_HZ 1
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#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
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#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ
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#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE
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#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ
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#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
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#define QEMU_FLASH0_BASE 0x00000000
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#define QEMU_FLASH0_SIZE 0x10000000
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#define QEMU_FLASH1_BASE 0x10000000
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#define QEMU_FLASH1_SIZE 0x10000000
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#define PLAT_QEMU_FIP_BASE 0x00008000
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#define PLAT_QEMU_FIP_MAX_SIZE 0x00020000
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/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */
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#define DEVICE0_BASE 0x40000000
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#define DEVICE0_SIZE 0x04080000
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/* This is map from NORMAL_UART up to SECURE_UART_MM */
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#define DEVICE1_BASE 0x60000000
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#define DEVICE1_SIZE 0x00041000
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/*
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* GIC related constants
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* We use GICv3 where CPU Interface registers are not memory mapped
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*/
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#define GICD_BASE 0x40060000
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#define GICR_BASE 0x40080000
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#define GICC_BASE 0x0
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#define QEMU_IRQ_SEC_SGI_0 8
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#define QEMU_IRQ_SEC_SGI_1 9
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#define QEMU_IRQ_SEC_SGI_2 10
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#define QEMU_IRQ_SEC_SGI_3 11
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#define QEMU_IRQ_SEC_SGI_4 12
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#define QEMU_IRQ_SEC_SGI_5 13
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#define QEMU_IRQ_SEC_SGI_6 14
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#define QEMU_IRQ_SEC_SGI_7 15
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE)
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#define PLATFORM_G0_PROPS(grp)
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/*
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* DT related constants
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*/
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#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
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#define PLAT_QEMU_DT_MAX_SIZE 0x10000
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
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#endif /* __PLATFORM_DEF_H__ */
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