417 lines
12 KiB
C
417 lines
12 KiB
C
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <cortex_a57.h>
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#include <denver.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <mce.h>
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#include <smmu.h>
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#include <stdbool.h>
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#include <t18x_ari.h>
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#include <tegra186_private.h>
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#include <tegra_private.h>
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extern void memcpy16(void *dest, const void *src, unsigned int length);
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/* state id mask */
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#define TEGRA186_STATE_ID_MASK 0xFU
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/* constants to get power state's wake time */
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#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U
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#define TEGRA186_WAKE_TIME_SHIFT 4U
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/* default core wake mask for CPU_SUSPEND */
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#define TEGRA186_CORE_WAKE_MASK 0x180cU
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/* context size to save during system suspend */
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#define TEGRA186_SE_CONTEXT_SIZE 3U
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static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
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static struct tegra_psci_percpu_data {
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uint32_t wake_time;
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} __aligned(CACHE_WRITEBACK_GRANULE) tegra_percpu_data[PLATFORM_CORE_COUNT];
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int32_t tegra_soc_validate_power_state(uint32_t power_state,
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psci_power_state_t *req_state)
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{
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uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK;
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uint32_t cpu = plat_my_core_pos();
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int32_t ret = PSCI_E_SUCCESS;
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/* save the core wake time (in TSC ticks)*/
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tegra_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK)
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<< TEGRA186_WAKE_TIME_SHIFT;
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/*
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* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
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* the correct value is read in tegra_soc_pwr_domain_suspend(), which
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* is called with caches disabled. It is possible to read a stale value
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* from DRAM in that function, because the L2 cache is not flushed
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* unless the cluster is entering CC6/CC7.
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*/
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clean_dcache_range((uint64_t)&tegra_percpu_data[cpu],
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sizeof(tegra_percpu_data[cpu]));
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/* Sanity check the requested state id */
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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case PSTATE_ID_CORE_POWERDN:
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/* Core powerdown request */
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
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break;
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default:
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ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
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ret = PSCI_E_INVALID_PARAMS;
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break;
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}
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return ret;
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}
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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const plat_local_state_t *pwr_domain_state;
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uint8_t stateid_afflvl0, stateid_afflvl2;
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uint32_t cpu = plat_my_core_pos();
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const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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mce_cstate_info_t cstate_info = { 0 };
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uint64_t smmu_ctx_base;
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uint32_t val;
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/* get the state ID */
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pwr_domain_state = target_state->pwr_domain_state;
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stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
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TEGRA186_STATE_ID_MASK;
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stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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TEGRA186_STATE_ID_MASK;
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if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
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(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
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/* Enter CPU idle/powerdown */
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val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
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(uint32_t)TEGRA_ARI_CORE_C6 : (uint32_t)TEGRA_ARI_CORE_C7;
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(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
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tegra_percpu_data[cpu].wake_time, 0U);
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} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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/* save SE registers */
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se_regs[0] = mmio_read_32(TEGRA_SE0_BASE +
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SE_MUTEX_WATCHDOG_NS_LIMIT);
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se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE +
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RNG_MUTEX_WATCHDOG_NS_LIMIT);
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se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE +
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PKA_MUTEX_WATCHDOG_NS_LIMIT);
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/* save 'Secure Boot' Processor Feature Config Register */
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val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
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/* save SMMU context to TZDRAM */
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smmu_ctx_base = params_from_bl2->tzdram_base +
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tegra186_get_smmu_ctx_offset();
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tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
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/* Prepare for system suspend */
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cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
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cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC7;
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cstate_info.system_state_force = 1;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Loop until system suspend is allowed */
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do {
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val = (uint32_t)mce_command_handler(
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(uint64_t)MCE_CMD_IS_SC7_ALLOWED,
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(uint64_t)TEGRA_ARI_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0U);
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} while (val == 0U);
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/* Instruct the MCE to enter system suspend state */
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(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
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/* set system suspend state for house-keeping */
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tegra186_set_system_suspend_entry();
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} else {
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; /* do nothing */
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Helper function to check if this is the last ON CPU in the cluster
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******************************************************************************/
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static bool tegra_last_cpu_in_cluster(const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target;
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bool last_on_cpu = true;
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uint32_t num_cpus = ncpu, pos = 0;
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do {
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target = states[pos];
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if (target != PLAT_MAX_OFF_STATE) {
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last_on_cpu = false;
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}
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--num_cpus;
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pos++;
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} while (num_cpus != 0U);
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return last_on_cpu;
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}
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/*******************************************************************************
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* Helper function to get target power state for the cluster
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******************************************************************************/
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static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states,
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uint32_t ncpu)
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{
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uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK;
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uint32_t cpu = plat_my_core_pos();
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int32_t ret;
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plat_local_state_t target = states[core_pos];
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mce_cstate_info_t cstate_info = { 0 };
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/* CPU suspend */
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if (target == PSTATE_ID_CORE_POWERDN) {
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/* Program default wake mask */
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cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Check if CCx state is allowed. */
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ret = mce_command_handler((uint64_t)MCE_CMD_IS_CCX_ALLOWED,
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(uint64_t)TEGRA_ARI_CORE_C7,
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tegra_percpu_data[cpu].wake_time,
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0U);
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if (ret == 0) {
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target = PSCI_LOCAL_STATE_RUN;
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}
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}
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/* CPU off */
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if (target == PLAT_MAX_OFF_STATE) {
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/* Enable cluster powerdn from last CPU in the cluster */
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if (tegra_last_cpu_in_cluster(states, ncpu)) {
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/* Enable CC7 state and turn off wake mask */
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cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Check if CCx state is allowed. */
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ret = mce_command_handler((uint64_t)MCE_CMD_IS_CCX_ALLOWED,
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(uint64_t)TEGRA_ARI_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0U);
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if (ret == 0) {
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target = PSCI_LOCAL_STATE_RUN;
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}
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} else {
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/* Turn off wake_mask */
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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target = PSCI_LOCAL_STATE_RUN;
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}
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}
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return target;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level
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******************************************************************************/
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
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uint32_t cpu = plat_my_core_pos();
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/* System Suspend */
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if ((lvl == (uint32_t)MPIDR_AFFLVL2) &&
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(states[cpu] == PSTATE_ID_SOC_POWERDN)) {
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target = PSTATE_ID_SOC_POWERDN;
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}
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/* CPU off, CPU suspend */
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if (lvl == (uint32_t)MPIDR_AFFLVL1) {
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target = tegra_get_afflvl1_pwr_state(states, ncpu);
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}
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/* target cluster/system state */
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return target;
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}
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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const plat_local_state_t *pwr_domain_state =
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target_state->pwr_domain_state;
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const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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TEGRA186_STATE_ID_MASK;
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uint64_t val;
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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/*
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* The TZRAM loses power when we enter system suspend. To
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* allow graceful exit from system suspend, we need to copy
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* BL3-1 over to TZDRAM.
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*/
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val = params_from_bl2->tzdram_base +
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tegra186_get_cpu_reset_handler_size();
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memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
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(uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
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}
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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int32_t ret = PSCI_E_SUCCESS;
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uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
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uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
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MPIDR_AFFINITY_BITS;
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if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) {
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ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr);
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ret = PSCI_E_NOT_PRESENT;
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} else {
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/* construct the target CPU # */
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target_cpu |= (target_cluster << 2);
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(void)mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U);
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}
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return ret;
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}
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int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
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uint8_t stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0];
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mce_cstate_info_t cstate_info = { 0 };
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uint64_t impl, val;
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/*
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* Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
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* A02p and beyond).
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*/
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if ((plat_params->l2_ecc_parity_prot_dis != 1) && (impl != DENVER_IMPL)) {
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val = read_l2ctlr_el1();
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val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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}
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/*
|
||
|
|
* Reset power state info for CPUs when onlining, we set
|
||
|
|
* deepest power when offlining a core but that may not be
|
||
|
|
* requested by non-secure sw which controls idle states. It
|
||
|
|
* will re-init this info from non-secure software when the
|
||
|
|
* core come online.
|
||
|
|
*/
|
||
|
|
if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) {
|
||
|
|
|
||
|
|
cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC1;
|
||
|
|
cstate_info.update_wake_mask = 1;
|
||
|
|
mce_update_cstate_info(&cstate_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check if we are exiting from deep sleep and restore SE
|
||
|
|
* context if we are.
|
||
|
|
*/
|
||
|
|
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
|
||
|
|
|
||
|
|
mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
|
||
|
|
se_regs[0]);
|
||
|
|
mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,
|
||
|
|
se_regs[1]);
|
||
|
|
mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT,
|
||
|
|
se_regs[2]);
|
||
|
|
|
||
|
|
/* Init SMMU */
|
||
|
|
tegra_smmu_init();
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Reset power state info for the last core doing SC7
|
||
|
|
* entry and exit, we set deepest power state as CC7
|
||
|
|
* and SC7 for SC7 entry which may not be requested by
|
||
|
|
* non-secure SW which controls idle states.
|
||
|
|
*/
|
||
|
|
cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
|
||
|
|
cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC1;
|
||
|
|
cstate_info.update_wake_mask = 1;
|
||
|
|
mce_update_cstate_info(&cstate_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
return PSCI_E_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
||
|
|
{
|
||
|
|
uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
|
||
|
|
|
||
|
|
(void)target_state;
|
||
|
|
|
||
|
|
/* Disable Denver's DCO operations */
|
||
|
|
if (impl == DENVER_IMPL) {
|
||
|
|
denver_disable_dco();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Turn off CPU */
|
||
|
|
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
|
||
|
|
(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
|
||
|
|
|
||
|
|
return PSCI_E_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
__dead2 void tegra_soc_prepare_system_off(void)
|
||
|
|
{
|
||
|
|
/* power off the entire system */
|
||
|
|
mce_enter_ccplex_state((uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF);
|
||
|
|
|
||
|
|
wfi();
|
||
|
|
|
||
|
|
/* wait for the system to power down */
|
||
|
|
for (;;) {
|
||
|
|
;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t tegra_soc_prepare_system_reset(void)
|
||
|
|
{
|
||
|
|
mce_enter_ccplex_state((uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT);
|
||
|
|
|
||
|
|
return PSCI_E_SUCCESS;
|
||
|
|
}
|