565 lines
15 KiB
C
565 lines
15 KiB
C
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <denver.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <mce_private.h>
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#include <t18x_ari.h>
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/*******************************************************************************
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* Register offsets for ARI request/results
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******************************************************************************/
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#define ARI_REQUEST 0x0U
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#define ARI_REQUEST_EVENT_MASK 0x4U
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#define ARI_STATUS 0x8U
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#define ARI_REQUEST_DATA_LO 0xCU
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#define ARI_REQUEST_DATA_HI 0x10U
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#define ARI_RESPONSE_DATA_LO 0x14U
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#define ARI_RESPONSE_DATA_HI 0x18U
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/* Status values for the current request */
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#define ARI_REQ_PENDING 1U
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#define ARI_REQ_ONGOING 3U
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#define ARI_REQUEST_VALID_BIT (1U << 8)
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#define ARI_EVT_MASK_STANDBYWFI_BIT (1U << 7)
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/* default timeout (us) to wait for ARI completion */
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#define ARI_MAX_RETRY_COUNT U(2000000)
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/*******************************************************************************
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* ARI helper functions
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******************************************************************************/
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static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg)
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{
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return mmio_read_32((uint64_t)ari_base + (uint64_t)reg);
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}
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static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg)
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{
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mmio_write_32((uint64_t)ari_base + (uint64_t)reg, val);
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}
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static inline uint32_t ari_get_request_low(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_REQUEST_DATA_LO);
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}
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static inline uint32_t ari_get_request_high(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_REQUEST_DATA_HI);
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}
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static inline uint32_t ari_get_response_low(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_RESPONSE_DATA_LO);
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}
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static inline uint32_t ari_get_response_high(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_RESPONSE_DATA_HI);
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}
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static inline void ari_clobber_response(uint32_t ari_base)
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{
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ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_LO);
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ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_HI);
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}
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static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
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uint32_t lo, uint32_t hi)
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{
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uint32_t retries = (uint32_t)ARI_MAX_RETRY_COUNT;
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uint32_t status;
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int32_t ret = 0;
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/* program the request, event_mask, hi and lo registers */
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ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO);
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ari_write_32(ari_base, hi, ARI_REQUEST_DATA_HI);
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ari_write_32(ari_base, evt_mask, ARI_REQUEST_EVENT_MASK);
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ari_write_32(ari_base, req | ARI_REQUEST_VALID_BIT, ARI_REQUEST);
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/*
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* For commands that have an event trigger, we should bypass
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* ARI_STATUS polling, since MCE is waiting for SW to trigger
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* the event.
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*/
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if (evt_mask != 0U) {
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ret = 0;
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} else {
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/* For shutdown/reboot commands, we dont have to check for timeouts */
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if ((req == TEGRA_ARI_MISC_CCPLEX) &&
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((lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
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(lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
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ret = 0;
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} else {
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/*
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* Wait for the command response for not more than the timeout
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*/
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while (retries != 0U) {
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/* read the command status */
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status = ari_read_32(ari_base, ARI_STATUS);
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if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U) {
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break;
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}
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/* delay 1 us */
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udelay(1);
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/* decrement the retry count */
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retries--;
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}
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/* assert if the command timed out */
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if (retries == 0U) {
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ERROR("ARI request timed out: req %d on CPU %d\n",
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req, plat_my_core_pos());
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assert(retries != 0U);
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}
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}
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}
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return ret;
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}
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int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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int32_t ret = 0;
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/* check for allowed power state */
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if ((state != TEGRA_ARI_CORE_C0) &&
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(state != TEGRA_ARI_CORE_C1) &&
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(state != TEGRA_ARI_CORE_C6) &&
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(state != TEGRA_ARI_CORE_C7)) {
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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ret = EINVAL;
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} else {
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
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ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
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(uint32_t)TEGRA_ARI_ENTER_CSTATE, state, wake_time);
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}
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return ret;
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}
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int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask)
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{
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uint64_t val = 0U;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* update CLUSTER_CSTATE? */
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if (cluster != 0U) {
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val |= (cluster & CLUSTER_CSTATE_MASK) |
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CLUSTER_CSTATE_UPDATE_BIT;
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}
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/* update CCPLEX_CSTATE? */
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if (ccplex != 0U) {
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val |= ((ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
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CCPLEX_CSTATE_UPDATE_BIT;
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}
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/* update SYSTEM_CSTATE? */
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if (system != 0U) {
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val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
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(((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
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SYSTEM_CSTATE_UPDATE_BIT);
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}
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/* update wake mask value? */
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if (update_wake_mask != 0U) {
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val |= CSTATE_WAKE_MASK_UPDATE_BIT;
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}
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/* set the updated cstate info */
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return ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_UPDATE_CSTATE_INFO,
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(uint32_t)val, wake_mask);
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}
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int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
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{
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int32_t ret = 0;
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/* sanity check crossover type */
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if ((type == TEGRA_ARI_CROSSOVER_C1_C6) ||
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(type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) {
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ret = EINVAL;
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} else {
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* update crossover threshold time */
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ret = ari_request_wait(ari_base, 0U,
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(uint32_t)TEGRA_ARI_UPDATE_CROSSOVER, type, time);
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}
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return ret;
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}
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uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state)
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{
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int32_t ret;
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uint64_t result;
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/* sanity check crossover type */
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if (state == 0U) {
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result = EINVAL;
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} else {
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0U,
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(uint32_t)TEGRA_ARI_CSTATE_STATS, state, 0U);
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if (ret != 0) {
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result = EINVAL;
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} else {
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result = (uint64_t)ari_get_response_low(ari_base);
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}
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}
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return result;
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}
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int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* write the cstate stats */
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return ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_WRITE_CSTATE_STATS,
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state, stats);
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}
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uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
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{
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uint64_t resp;
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int32_t ret;
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uint32_t local_data = data;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* ARI_REQUEST_DATA_HI is reserved for commands other than 'ECHO' */
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if (cmd != TEGRA_ARI_MISC_ECHO) {
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local_data = 0U;
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}
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ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_MISC, cmd, local_data);
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if (ret != 0) {
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resp = (uint64_t)ret;
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} else {
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/* get the command response */
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resp = ari_get_response_low(ari_base);
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resp |= ((uint64_t)ari_get_response_high(ari_base) << 32);
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}
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return resp;
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}
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int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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int32_t ret;
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uint32_t result;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_IS_CCX_ALLOWED,
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state & 0x7U, wake_time);
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if (ret != 0) {
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ERROR("%s: failed (%d)\n", __func__, ret);
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result = 0U;
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} else {
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result = ari_get_response_low(ari_base) & 0x1U;
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}
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/* 1 = CCx allowed, 0 = CCx not allowed */
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return (int32_t)result;
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}
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int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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int32_t ret, result;
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/* check for allowed power state */
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if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) &&
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(state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) {
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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result = EINVAL;
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} else {
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0U,
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(uint32_t)TEGRA_ARI_IS_SC7_ALLOWED, state, wake_time);
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if (ret != 0) {
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ERROR("%s: failed (%d)\n", __func__, ret);
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result = 0;
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} else {
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/* 1 = SC7 allowed, 0 = SC7 not allowed */
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result = (ari_get_response_low(ari_base) != 0U) ? 1 : 0;
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}
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}
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return result;
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}
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int32_t ari_online_core(uint32_t ari_base, uint32_t core)
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{
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uint64_t cpu = read_mpidr() & (MPIDR_CPU_MASK);
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uint64_t cluster = (read_mpidr() & (MPIDR_CLUSTER_MASK)) >>
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(MPIDR_AFFINITY_BITS);
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uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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int32_t ret;
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/* construct the current CPU # */
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cpu |= (cluster << 2);
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/* sanity check target core id */
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if ((core >= MCE_CORE_ID_MAX) || (cpu == (uint64_t)core)) {
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ERROR("%s: unsupported core id (%d)\n", __func__, core);
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ret = EINVAL;
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} else {
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/*
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* The Denver cluster has 2 CPUs only - 0, 1.
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*/
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if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) {
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ERROR("%s: unknown core id (%d)\n", __func__, core);
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ret = EINVAL;
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} else {
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0U,
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(uint32_t)TEGRA_ARI_ONLINE_CORE, core, 0U);
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}
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}
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return ret;
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}
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int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
|
||
|
|
{
|
||
|
|
uint32_t val;
|
||
|
|
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If the enable bit is cleared, Auto-CC3 will be disabled by setting
|
||
|
|
* the SW visible voltage/frequency request registers for all non
|
||
|
|
* floorswept cores valid independent of StandbyWFI and disabling
|
||
|
|
* the IDLE voltage/frequency request register. If set, Auto-CC3
|
||
|
|
* will be enabled by setting the ARM SW visible voltage/frequency
|
||
|
|
* request registers for all non floorswept cores to be enabled by
|
||
|
|
* StandbyWFI or the equivalent signal, and always keeping the IDLE
|
||
|
|
* voltage/frequency request register enabled.
|
||
|
|
*/
|
||
|
|
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
|
||
|
|
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
|
||
|
|
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
|
||
|
|
|
||
|
|
return ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_CC3_CTRL, val, 0U);
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ari_reset_vector_update(uint32_t ari_base)
|
||
|
|
{
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Need to program the CPU reset vector one time during cold boot
|
||
|
|
* and SC7 exit
|
||
|
|
*/
|
||
|
|
(void)ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ari_roc_flush_cache_trbits(uint32_t ari_base)
|
||
|
|
{
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
return ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, 0U, 0U);
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ari_roc_flush_cache(uint32_t ari_base)
|
||
|
|
{
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
return ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, 0U, 0U);
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ari_roc_clean_cache(uint32_t ari_base)
|
||
|
|
{
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
return ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, 0U, 0U);
|
||
|
|
}
|
||
|
|
|
||
|
|
uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
|
||
|
|
{
|
||
|
|
uint64_t mca_arg_data, result = 0;
|
||
|
|
uint32_t resp_lo, resp_hi;
|
||
|
|
uint32_t mca_arg_err, mca_arg_finish;
|
||
|
|
int32_t ret;
|
||
|
|
|
||
|
|
/* Set data (write) */
|
||
|
|
mca_arg_data = (data != NULL) ? *data : 0ULL;
|
||
|
|
|
||
|
|
/* Set command */
|
||
|
|
ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO);
|
||
|
|
ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI);
|
||
|
|
|
||
|
|
ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_MCA,
|
||
|
|
(uint32_t)mca_arg_data,
|
||
|
|
(uint32_t)(mca_arg_data >> 32U));
|
||
|
|
if (ret == 0) {
|
||
|
|
resp_lo = ari_get_response_low(ari_base);
|
||
|
|
resp_hi = ari_get_response_high(ari_base);
|
||
|
|
|
||
|
|
mca_arg_err = resp_lo & MCA_ARG_ERROR_MASK;
|
||
|
|
mca_arg_finish = (resp_hi >> MCA_ARG_FINISH_SHIFT) &
|
||
|
|
MCA_ARG_FINISH_MASK;
|
||
|
|
|
||
|
|
if (mca_arg_finish == 0U) {
|
||
|
|
result = (uint64_t)mca_arg_err;
|
||
|
|
} else {
|
||
|
|
if (data != NULL) {
|
||
|
|
resp_lo = ari_get_request_low(ari_base);
|
||
|
|
resp_hi = ari_get_request_high(ari_base);
|
||
|
|
*data = ((uint64_t)resp_hi << 32U) |
|
||
|
|
(uint64_t)resp_lo;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
|
||
|
|
{
|
||
|
|
int32_t ret = 0;
|
||
|
|
/* sanity check GSC ID */
|
||
|
|
if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX) {
|
||
|
|
ret = EINVAL;
|
||
|
|
} else {
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The MCE code will read the GSC carveout value, corrseponding to
|
||
|
|
* the ID, from the MC registers and update the internal GSC registers
|
||
|
|
* of the CCPLEX.
|
||
|
|
*/
|
||
|
|
(void)ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
|
||
|
|
{
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The MCE will shutdown or restart the entire system
|
||
|
|
*/
|
||
|
|
(void)ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
|
||
|
|
uint64_t *data)
|
||
|
|
{
|
||
|
|
int32_t ret, result;
|
||
|
|
uint32_t val, req_status;
|
||
|
|
uint8_t req_cmd;
|
||
|
|
|
||
|
|
req_cmd = (uint8_t)(req & UNCORE_PERFMON_CMD_MASK);
|
||
|
|
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
|
||
|
|
/* sanity check input parameters */
|
||
|
|
if ((req_cmd == UNCORE_PERFMON_CMD_READ) && (data == NULL)) {
|
||
|
|
ERROR("invalid parameters\n");
|
||
|
|
result = EINVAL;
|
||
|
|
} else {
|
||
|
|
/*
|
||
|
|
* For "write" commands get the value that has to be written
|
||
|
|
* to the uncore perfmon registers
|
||
|
|
*/
|
||
|
|
val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ?
|
||
|
|
(uint32_t)*data : 0U;
|
||
|
|
|
||
|
|
ret = ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_PERFMON, val, (uint32_t)req);
|
||
|
|
if (ret != 0) {
|
||
|
|
result = ret;
|
||
|
|
} else {
|
||
|
|
/* read the command status value */
|
||
|
|
req_status = ari_get_response_high(ari_base) &
|
||
|
|
UNCORE_PERFMON_RESP_STATUS_MASK;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* For "read" commands get the data from the uncore
|
||
|
|
* perfmon registers
|
||
|
|
*/
|
||
|
|
req_status &= UNCORE_PERFMON_RESP_STATUS_MASK;
|
||
|
|
if ((req_status == 0U) && (req_cmd == UNCORE_PERFMON_CMD_READ)) {
|
||
|
|
*data = ari_get_response_low(ari_base);
|
||
|
|
}
|
||
|
|
result = (int32_t)req_status;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* This invokes the ARI_MISC_CCPLEX commands. This can be
|
||
|
|
* used to enable/disable coresight clock gating.
|
||
|
|
*/
|
||
|
|
|
||
|
|
if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) ||
|
||
|
|
((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
|
||
|
|
(value > 1U))) {
|
||
|
|
ERROR("%s: invalid parameters \n", __func__);
|
||
|
|
} else {
|
||
|
|
/* clean the previous response state */
|
||
|
|
ari_clobber_response(ari_base);
|
||
|
|
(void)ari_request_wait(ari_base, 0U,
|
||
|
|
(uint32_t)TEGRA_ARI_MISC_CCPLEX, index, value);
|
||
|
|
}
|
||
|
|
}
|