379 lines
8.5 KiB
C
379 lines
8.5 KiB
C
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <s10_mailbox.h>
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#include <tools_share/uuid.h>
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/* Number of SiP Calls implemented */
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#define SIP_NUM_CALLS 0x3
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/* Total buffer the driver can hold */
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#define FPGA_CONFIG_BUFFER_SIZE 4
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int current_block;
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int current_buffer;
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int current_id = 1;
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int max_blocks;
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uint32_t bytes_per_block;
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uint32_t blocks_submitted;
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uint32_t blocks_completed;
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struct fpga_config_info {
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uint32_t addr;
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int size;
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int size_written;
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uint32_t write_requested;
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int subblocks_sent;
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int block_number;
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};
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/* SiP Service UUID */
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DEFINE_SVC_UUID2(intl_svc_uid,
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0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
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0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
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uint64_t plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
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static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
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{
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uint32_t args[3];
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while (max_blocks > 0 && buffer->size > buffer->size_written) {
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if (buffer->size - buffer->size_written <=
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bytes_per_block) {
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args[0] = (1<<8);
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args[1] = buffer->addr + buffer->size_written;
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args[2] = buffer->size - buffer->size_written;
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buffer->size_written +=
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buffer->size - buffer->size_written;
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buffer->subblocks_sent++;
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mailbox_send_cmd_async(0x4,
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MBOX_RECONFIG_DATA,
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args, 3, 0);
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current_buffer++;
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current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
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} else {
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args[0] = (1<<8);
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args[1] = buffer->addr + buffer->size_written;
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args[2] = bytes_per_block;
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buffer->size_written += bytes_per_block;
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mailbox_send_cmd_async(0x4,
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MBOX_RECONFIG_DATA,
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args, 3, 0);
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buffer->subblocks_sent++;
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}
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max_blocks--;
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}
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}
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static int intel_fpga_sdm_write_all(void)
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{
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int i;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
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intel_fpga_sdm_write_buffer(
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&fpga_config_buffers[current_buffer]);
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return 0;
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}
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uint32_t intel_mailbox_fpga_config_isdone(void)
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{
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uint32_t args[2];
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uint32_t response[6];
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int status;
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status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0,
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response);
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if (status < 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (response[RECONFIG_STATUS_STATE] &&
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response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS))
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return INTEL_SIP_SMC_STATUS_ERROR;
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if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
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SOFTFUNC_STATUS_SEU_ERROR)
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return INTEL_SIP_SMC_STATUS_ERROR;
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if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
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SOFTFUNC_STATUS_CONF_DONE) &&
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(response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
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SOFTFUNC_STATUS_INIT_DONE))
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return INTEL_SIP_SMC_STATUS_OK;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
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{
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int i;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (fpga_config_buffers[i].block_number == current_block) {
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fpga_config_buffers[i].subblocks_sent--;
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if (fpga_config_buffers[i].subblocks_sent == 0
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&& fpga_config_buffers[i].size <=
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fpga_config_buffers[i].size_written) {
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fpga_config_buffers[i].write_requested = 0;
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current_block++;
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*buffer_addr_completed =
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fpga_config_buffers[i].addr;
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return 0;
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}
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}
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}
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return -1;
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}
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unsigned int address_in_ddr(uint32_t *addr)
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{
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if (((unsigned long long)addr > DRAM_BASE) &&
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((unsigned long long)addr < DRAM_BASE + DRAM_SIZE))
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return 0;
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return -1;
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}
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int intel_fpga_config_completed_write(uint32_t *completed_addr,
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uint32_t *count)
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{
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uint32_t status = INTEL_SIP_SMC_STATUS_OK;
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*count = 0;
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int resp_len = 0;
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uint32_t resp[5];
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int all_completed = 1;
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int count_check = 0;
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if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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for (count_check = 0; count_check < 3; count_check++)
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if (address_in_ddr(&completed_addr[*count + count_check]) != 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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resp_len = mailbox_read_response(0x4, resp);
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while (resp_len >= 0 && *count < 3) {
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max_blocks++;
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if (mark_last_buffer_xfer_completed(
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&completed_addr[*count]) == 0)
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*count = *count + 1;
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else
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break;
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resp_len = mailbox_read_response(0x4, resp);
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}
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if (*count <= 0) {
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if (resp_len != MBOX_NO_RESPONSE &&
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resp_len != MBOX_TIMEOUT && resp_len != 0) {
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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*count = 0;
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}
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intel_fpga_sdm_write_all();
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if (*count > 0)
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status = INTEL_SIP_SMC_STATUS_OK;
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else if (*count == 0)
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status = INTEL_SIP_SMC_STATUS_BUSY;
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (fpga_config_buffers[i].write_requested != 0) {
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all_completed = 0;
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break;
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}
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}
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if (all_completed == 1)
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return INTEL_SIP_SMC_STATUS_OK;
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return status;
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}
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int intel_fpga_config_start(uint32_t config_type)
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{
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uint32_t response[3];
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int status = 0;
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status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0,
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response);
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if (status < 0)
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return status;
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max_blocks = response[0];
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bytes_per_block = response[1];
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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fpga_config_buffers[i].size = 0;
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fpga_config_buffers[i].size_written = 0;
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fpga_config_buffers[i].addr = 0;
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fpga_config_buffers[i].write_requested = 0;
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fpga_config_buffers[i].block_number = 0;
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fpga_config_buffers[i].subblocks_sent = 0;
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}
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blocks_submitted = 0;
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current_block = 0;
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current_buffer = 0;
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return 0;
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}
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uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
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{
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int i = 0;
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uint32_t status = INTEL_SIP_SMC_STATUS_OK;
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if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE)
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status = INTEL_SIP_SMC_STATUS_REJECTED;
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if (mem + size > DRAM_BASE + DRAM_SIZE)
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status = INTEL_SIP_SMC_STATUS_REJECTED;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (!fpga_config_buffers[i].write_requested) {
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fpga_config_buffers[i].addr = mem;
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fpga_config_buffers[i].size = size;
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fpga_config_buffers[i].size_written = 0;
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fpga_config_buffers[i].write_requested = 1;
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fpga_config_buffers[i].block_number =
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blocks_submitted++;
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fpga_config_buffers[i].subblocks_sent = 0;
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break;
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}
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}
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if (i == FPGA_CONFIG_BUFFER_SIZE) {
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status = INTEL_SIP_SMC_STATUS_REJECTED;
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return status;
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} else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) {
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status = INTEL_SIP_SMC_STATUS_BUSY;
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}
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intel_fpga_sdm_write_all();
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return status;
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}
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/*
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* This function is responsible for handling all SiP calls from the NS world
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*/
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uintptr_t sip_smc_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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uint32_t status = INTEL_SIP_SMC_STATUS_OK;
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uint32_t completed_addr[3];
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uint32_t count = 0;
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switch (smc_fid) {
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case SIP_SVC_UID:
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/* Return UID to the caller */
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SMC_UUID_RET(handle, intl_svc_uid);
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break;
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case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
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status = intel_mailbox_fpga_config_isdone();
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SMC_RET4(handle, status, 0, 0, 0);
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break;
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case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
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SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
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INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
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INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
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INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
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break;
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case INTEL_SIP_SMC_FPGA_CONFIG_START:
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status = intel_fpga_config_start(x1);
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SMC_RET4(handle, status, 0, 0, 0);
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break;
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case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
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status = intel_fpga_config_write(x1, x2);
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SMC_RET4(handle, status, 0, 0, 0);
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break;
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case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
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status = intel_fpga_config_completed_write(completed_addr,
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&count);
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switch (count) {
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case 1:
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SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
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completed_addr[0], 0, 0);
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break;
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case 2:
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SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
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completed_addr[0],
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completed_addr[1], 0);
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break;
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case 3:
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SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
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completed_addr[0],
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completed_addr[1],
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completed_addr[2]);
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break;
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case 0:
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SMC_RET4(handle, status, 0, 0, 0);
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break;
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default:
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SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
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}
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break;
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default:
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return plat_sip_handler(smc_fid, x1, x2, x3, x4,
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cookie, handle, flags);
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}
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}
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DECLARE_RT_SVC(
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s10_sip_svc,
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OEN_SIP_START,
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OEN_SIP_END,
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SMC_TYPE_FAST,
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NULL,
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sip_smc_handler
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);
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DECLARE_RT_SVC(
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s10_sip_svc_std,
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OEN_SIP_START,
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OEN_SIP_END,
|
||
|
|
SMC_TYPE_YIELD,
|
||
|
|
NULL,
|
||
|
|
sip_smc_handler
|
||
|
|
);
|