88 lines
3.5 KiB
C
88 lines
3.5 KiB
C
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __S10_RESETMANAGER_H__
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#define __S10_RESETMANAGER_H__
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#define S10_RSTMGR_PER0MODRST 0xffd11024
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#define S10_RSTMGR_PER1MODRST 0xffd11028
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#define S10_RSTMGR_HDSKEN 0xffd11010
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#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
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#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
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#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
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#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
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#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
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#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000
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#define S10_RSTMGR_PER0MODRST_DMA 0x00010000
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#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
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#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
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#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
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#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
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#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000
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#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000
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#define S10_RSTMGR_PER0MODRST_NAND 0x00000020
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#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
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#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080
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#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000
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#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000
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#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000
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#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000
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#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800
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#define S10_RSTMGR_PER0MODRST_USB0 0x00000008
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#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000
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#define S10_RSTMGR_PER0MODRST_USB1 0x00000010
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#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1
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#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2
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#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4
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#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8
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#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
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#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
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#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
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#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
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#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
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#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
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#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
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#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
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#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
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#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
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#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
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#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
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#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
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#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
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#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
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#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
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#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
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#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
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#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
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#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
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#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
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#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
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#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
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#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
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#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
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#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
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#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
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#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
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#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
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#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
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#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000
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#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000
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#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000
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#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000
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#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000
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#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000
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#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000
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#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000
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void deassert_peripheral_reset(void);
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void config_hps_hs_before_warm_reset(void);
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#endif
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