327 lines
11 KiB
C
327 lines
11 KiB
C
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat_imx8.h>
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#include <sci/sci.h>
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#include "../../common/sci/imx8_mu.h"
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#define CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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const static int ap_core_index[PLATFORM_CORE_COUNT] = {
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SC_R_A53_0, SC_R_A53_1, SC_R_A53_2,
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SC_R_A53_3, SC_R_A72_0, SC_R_A72_1,
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};
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/* save gic dist/redist context when GIC is poewr down */
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static struct plat_gic_ctx imx_gicv3_ctx;
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static unsigned int gpt_lpcg, gpt_reg[2];
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static void imx_enable_irqstr_wakeup(void)
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{
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uint32_t irq_mask;
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gicv3_dist_ctx_t *dist_ctx = &imx_gicv3_ctx.dist_ctx;
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/* put IRQSTR into ON mode */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_ON);
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/* enable the irqsteer to handle wakeup irq */
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mmio_write_32(IMX_WUP_IRQSTR_BASE, 0x1);
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for (int i = 0; i < 15; i++) {
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irq_mask = dist_ctx->gicd_isenabler[i];
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mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x3c - 0x4 * i, irq_mask);
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}
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/* set IRQSTR low power mode */
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if (imx_is_wakeup_src_irqsteer())
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_STBY);
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else
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF);
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}
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static void imx_disable_irqstr_wakeup(void)
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{
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/* put IRQSTR into ON from STBY mode */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_ON);
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/* disable the irqsteer */
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mmio_write_32(IMX_WUP_IRQSTR_BASE, 0x0);
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for (int i = 0; i < 16; i++)
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mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x4 + 0x4 * i, 0x0);
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/* put IRQSTR into OFF mode */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF);
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}
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int imx_pwr_domain_on(u_register_t mpidr)
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{
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int ret = PSCI_E_SUCCESS;
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unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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sc_pm_set_resource_power_mode(ipc_handle, cluster_id == 0 ?
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SC_R_A53 : SC_R_A72, SC_PM_PW_MODE_ON);
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if (cluster_id == 1)
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON);
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if (sc_pm_set_resource_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
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ERROR("core %d power on failed!\n", cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id);
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ret = PSCI_E_INTERN_FAIL;
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}
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if (sc_pm_cpu_start(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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true, BL31_BASE) != SC_ERR_NONE) {
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ERROR("boot core %d failed!\n", cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id);
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ret = PSCI_E_INTERN_FAIL;
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}
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return ret;
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}
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void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint64_t mpidr = read_mpidr_el1();
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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plat_gic_pcpu_init();
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plat_gic_cpuif_enable();
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}
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void imx_pwr_domain_off(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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plat_gic_cpuif_disable();
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sc_pm_req_cpu_low_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE);
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
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cci_disable_snoop_dvm_reqs(cluster_id);
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if (cluster_id == 1)
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF);
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}
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printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id);
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}
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void imx_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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plat_gic_cpuif_disable();
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sc_pm_set_cpu_resume(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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true, BL31_BASE);
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sc_pm_req_cpu_low_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC);
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} else {
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dsb();
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write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
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isb();
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}
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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if (cluster_id == 1)
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF);
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}
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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plat_gic_cpuif_disable();
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/* save gic context */
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plat_gic_save(cpu_id, &imx_gicv3_ctx);
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/* enable the irqsteer for wakeup */
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imx_enable_irqstr_wakeup();
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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/* Put GIC in LP mode. */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_OFF);
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/* Save GPT clock and registers, then turn off its power */
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gpt_lpcg = mmio_read_32(IMX_GPT_LPCG_BASE);
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gpt_reg[0] = mmio_read_32(IMX_GPT_BASE);
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gpt_reg[1] = mmio_read_32(IMX_GPT_BASE + 0x4);
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_OFF);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_OFF);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF);
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sc_pm_set_cpu_resume(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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true, BL31_BASE);
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if (imx_is_wakeup_src_irqsteer())
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sc_pm_req_cpu_low_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_IRQSTEER);
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else
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sc_pm_req_cpu_low_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_SCU);
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}
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}
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void imx_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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/* check the system level status */
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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MU_Resume(SC_IPC_BASE);
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sc_pm_req_cpu_low_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC);
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/* Put GIC/IRQSTR back to high power mode. */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_ON);
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/* Turn GPT power and restore its clock and registers */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
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sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
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mmio_write_32(IMX_GPT_BASE, gpt_reg[0]);
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mmio_write_32(IMX_GPT_BASE + 0x4, gpt_reg[1]);
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mmio_write_32(IMX_GPT_LPCG_BASE, gpt_lpcg);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_ON);
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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/* restore gic context */
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plat_gic_restore(cpu_id, &imx_gicv3_ctx);
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/* disable the irqsteer wakeup */
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imx_disable_irqstr_wakeup();
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plat_gic_cpuif_enable();
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}
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/* check the cluster level power status */
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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if (cluster_id == 1)
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON);
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}
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/* check the core level power status */
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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sc_pm_set_cpu_resume(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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false, BL31_BASE);
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sc_pm_req_cpu_low_power_mode(ipc_handle,
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ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id],
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SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC);
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plat_gic_cpuif_enable();
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} else {
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write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
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isb();
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}
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}
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int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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return PSCI_E_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const plat_psci_ops_t imx_plat_psci_ops = {
|
||
|
|
.pwr_domain_on = imx_pwr_domain_on,
|
||
|
|
.pwr_domain_on_finish = imx_pwr_domain_on_finish,
|
||
|
|
.pwr_domain_off = imx_pwr_domain_off,
|
||
|
|
.pwr_domain_suspend = imx_domain_suspend,
|
||
|
|
.pwr_domain_suspend_finish = imx_domain_suspend_finish,
|
||
|
|
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
|
||
|
|
.validate_power_state = imx_validate_power_state,
|
||
|
|
.validate_ns_entrypoint = imx_validate_ns_entrypoint,
|
||
|
|
.system_off = imx_system_off,
|
||
|
|
.system_reset = imx_system_reset,
|
||
|
|
};
|
||
|
|
|
||
|
|
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||
|
|
const plat_psci_ops_t **psci_ops)
|
||
|
|
{
|
||
|
|
imx_mailbox_init(sec_entrypoint);
|
||
|
|
*psci_ops = &imx_plat_psci_ops;
|
||
|
|
|
||
|
|
/* make sure system sources power ON in low power mode by default */
|
||
|
|
sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_ON);
|
||
|
|
|
||
|
|
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_DDR,
|
||
|
|
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_DDR,
|
||
|
|
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_MU,
|
||
|
|
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_MU,
|
||
|
|
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_INTERCONNECT,
|
||
|
|
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
|
||
|
|
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT,
|
||
|
|
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|