108 lines
3.4 KiB
C
108 lines
3.4 KiB
C
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX8M_GPC_H
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#define IMX8M_GPC_H
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#define LPCR_A53_BSC 0x0
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#define LPCR_A53_BSC2 0x108
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#define LPCR_A53_AD 0x4
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#define LPCR_M4 0x8
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#define SLPCR 0x14
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#define MST_CPU_MAPPING 0x18
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#define MLPCR 0x20
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#define PGC_ACK_SEL_A53 0x24
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#define IMR1_CORE0_A53 0x30
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#define IMR1_CORE1_A53 0x40
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#define IMR1_CORE2_A53 0x1C0
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#define IMR1_CORE3_A53 0x1D0
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#define IMR1_CORE0_M4 0x50
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#define SLT0_CFG 0xB0
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#define GPC_PU_PWRHSK 0x1FC
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#define PGC_CPU_0_1_MAPPING 0xEC
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#define CPU_PGC_UP_TRG 0xF0
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#define PU_PGC_UP_TRG 0xF8
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#define CPU_PGC_DN_TRG 0xFC
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#define PU_PGC_DN_TRG 0x104
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#define A53_CORE0_PGC 0x800
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#define A53_PLAT_PGC 0x900
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#define PLAT_PGC_PCR 0x900
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#define PGC_SCU_TIMING 0x910
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#define MASK_DSM_TRIGGER_A53 BIT(31)
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#define IRQ_SRC_A53_WUP BIT(30)
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#define IRQ_SRC_A53_WUP_SHIFT 30
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#define IRQ_SRC_C1 BIT(29)
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#define IRQ_SRC_C0 BIT(28)
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#define IRQ_SRC_C3 BIT(23)
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#define IRQ_SRC_C2 BIT(22)
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#define CPU_CLOCK_ON_LPM BIT(14)
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#define A53_CLK_ON_LPM BIT(14)
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#define MASTER0_LPM_HSK BIT(6)
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#define L2PGE BIT(31)
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#define EN_L2_WFI_PDN BIT(5)
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#define EN_PLAT_PDN BIT(4)
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#define SLPCR_EN_DSM BIT(31)
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#define SLPCR_RBC_EN BIT(30)
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#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
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#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
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#define SLPCR_VSTBY BIT(2)
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#define SLPCR_SBYOS BIT(1)
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#define SLPCR_BYPASS_PMIC_READY BIT(0)
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#define SLPCR_RBC_COUNT_SHIFT 24
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#define SLPCR_STBY_COUNT_SHFT 3
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#define A53_DUMMY_PDN_ACK BIT(15)
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#define A53_DUMMY_PUP_ACK BIT(31)
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#define A53_PLAT_PDN_ACK BIT(2)
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#define A53_PLAT_PUP_ACK BIT(18)
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#define PLAT_PUP_SLT_CTRL BIT(9)
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#define PLAT_PDN_SLT_CTRL BIT(8)
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#define SLT_PLAT_PDN BIT(8)
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#define SLT_PLAT_PUP BIT(9)
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#define MASTER1_MAPPING BIT(1)
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#define MASTER2_MAPPING BIT(2)
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/* helper macro */
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#define A53_LPM_MASK U(0xF)
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#define A53_LPM_WAIT U(0x5)
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#define A53_LPM_STOP U(0xA)
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#define LPM_MODE(local_state) ((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP)
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#define DSM_MODE_MASK BIT(31)
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#define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2))
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#define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40)
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#define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16))
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#define COREx_IRQ_WUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 + 20)))
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#define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21)))
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#define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4)))
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#define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2))
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#define IRQ_IMR_NUM 4
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#define IMR_MASK_ALL 0xffffffff
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/* function declare */
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void imx_gpc_init(void);
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void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint);
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void imx_set_cpu_pwr_off(unsigned int core_index);
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void imx_set_cpu_pwr_on(unsigned int core_index);
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void imx_set_cpu_lpm(unsigned int core_index, bool pdn);
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void imx_set_cluster_standby(bool retention);
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void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state);
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void imx_noc_slot_config(bool pdn);
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void imx_set_sys_wakeup(unsigned int last_core, bool pdn);
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void imx_set_sys_lpm(unsigned last_core, bool retention);
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void imx_set_rbc_count(void);
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void imx_clear_rbc_count(void);
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#endif /*IMX8M_GPC_H */
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