205 lines
6.1 KiB
C
205 lines
6.1 KiB
C
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define PICOPI_PRIMARY_CPU 0
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET 1
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF 2
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH 4
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#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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* i.MX7 has a 32 byte cacheline size
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* i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298
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*/
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#define CACHE_WRITEBACK_SHIFT 4
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*
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* Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
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*/
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#define BOOT_ROM_BASE 0x00000000
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#define BOOT_ROM_SIZE 0x00020000
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#define OCRAM_S_BASE 0x00180000
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#define OCRAM_S_SIZE 0x00008000
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/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
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#define DRAM_BASE 0x80000000
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#define DRAM_SIZE 0x20000000
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#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
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/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
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#define IMX7_OPTEE_SIZE 0x02000000
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#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
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#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
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/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
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#define BL2_RAM_SIZE 0x00100000
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#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
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#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
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/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
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#define SHARED_RAM_SIZE 0x00001000
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#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
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#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
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/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
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#define IMX7_UBOOT_SIZE 0x00100000
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#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
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#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
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/* Define FIP image absolute location 0x80000000 - 0x80100000 */
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#define IMX7_FIP_SIZE 0x00100000
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#define IMX7_FIP_BASE (DRAM_BASE)
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#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE)
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/* Define FIP image location at 1MB offset */
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#define IMX7_FIP_MMC_BASE (1024 * 1024)
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/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
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#define IMX7_DTB_SIZE 0x00100000
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#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
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#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
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/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
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#define IMX7_DTB_OVERLAY_SIZE 0x00001000
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#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
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#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
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IMX7_DTB_OVERLAY_SIZE)
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/*
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* BL2 specific defines.
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*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE BL2_RAM_BASE
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#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
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/*
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* BL3-2/OPTEE
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*/
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# define BL32_BASE IMX7_OPTEE_BASE
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# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
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/*
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* BL3-3/U-BOOT
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*/
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#define BL33_BASE IMX7_UBOOT_BASE
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#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
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/*
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* ATF's view of memory
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*
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* 0xa0000000 +-----------------+
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* | DDR | BL32/OPTEE
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* 0x9e000000 +-----------------+
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* | DDR | BL23 ATF
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* 0x9df00000 +-----------------+
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* | DDR | Shared MBOX RAM
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* 0x9de00000 +-----------------+
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* | DDR | Unallocated
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* 0x87900000 +-----------------+
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* | DDR | BL33/U-BOOT
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* 0x87800000 +-----------------+
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* | DDR | Unallocated
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* 0x83100000 +-----------------+
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* | DDR | DTB
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* 0x83000000 +-----------------+
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* | DDR | Unallocated
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* 0x80100000 +-----------------+
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* | DDR | FIP
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* 0x80000000 +-----------------+
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* | SOC I/0 |
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* 0x00a00000 +-----------------+
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* | OCRAM | Not used
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* 0x00900000 +-----------------+
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* | SOC I/0 |
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* 0x00188000 +-----------------+
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* | OCRAM_S | Not used
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* 0x00180000 +-----------------+
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* | SOC I/0 |
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* 0x00020000 +-----------------+
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* | BootROM | BL1
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* 0x00000000 +-----------------+
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_MMAP_REGIONS 10
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#define MAX_XLAT_TABLES 6
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#define MAX_IO_DEVICES 2
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#define MAX_IO_HANDLES 3
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#define MAX_IO_BLOCK_DEVICES 1
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/* UART defines */
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#define PLAT_IMX7_BOOT_UART_BASE MXC_UART5_BASE
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#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
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#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
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/* MMC defines */
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#ifndef PLAT_PICOPI_SD
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#define PLAT_PICOPI_SD 3
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#endif
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#if PLAT_PICOPI_SD == 1
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#define PLAT_PICOPI_BOOT_MMC_BASE USDHC1_BASE
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#endif /* PLAT_PICOPI_SD == 1 */
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#if PLAT_PICOPI_SD == 2
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#define PLAT_PICOPI_BOOT_MMC_BASE USDHC2_BASE
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#endif /* PLAT_PICOPI_SD == 2 */
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#if PLAT_PICOPI_SD == 3
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#define PLAT_PICOPI_BOOT_MMC_BASE USDHC3_BASE
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#endif /* PLAT_PICOPI_SD == 3 */
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
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#endif /* PLATFORM_DEF_H */
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