58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <imx_aips.h>
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#include <imx_regs.h>
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static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
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{
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int i;
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uintptr_t addr;
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/*
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* See section 4.7.7.1 AIPSTZ_MPR field descriptions
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
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* 0111 ->
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* 0: Write Access from master not buffered
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* 1: Master is trusted for read access
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* 1: Master is trsuted for write access
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* 1: Access from master is not forced to user mode
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*/
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addr = (uintptr_t)&aips_regs->aipstz_mpr;
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mmio_write_32(addr, 0x77777777);
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/*
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* Helpfully the OPACR registers have the logical inversion of the above
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* See section 4.7.7.1 AIPSTZ_MPR field descriptions
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
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* 0000 ->
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* 0: Write Access to the peripheral is not buffered by AIPSTZ
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* 0: The peripheral does not require supervisor priv to access
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* 0: Master is trsuted for write access
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* 0: Access from master is not forced to user mode
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*/
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for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
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addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
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mmio_write_32(addr, 0x00000000);
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}
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}
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void imx_aips_init(void)
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{
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int i;
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struct aipstz_regs *aips_regs[] = {
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(struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
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(struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
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(struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
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};
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for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
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imx_aips_set_default_access(aips_regs[i]);
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}
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