303 lines
9.9 KiB
C
303 lines
9.9 KiB
C
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_ARM_H
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#define PLAT_ARM_H
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#include <stdint.h>
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#include <drivers/arm/tzc_common.h>
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#include <lib/bakery_lock.h>
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#include <lib/cassert.h>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/spinlock.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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/*******************************************************************************
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* Forward declarations
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******************************************************************************/
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struct meminfo;
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struct image_info;
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struct bl_params;
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typedef struct arm_tzc_regions_info {
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unsigned long long base;
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unsigned long long end;
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unsigned int sec_attr;
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unsigned int nsaid_permissions;
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} arm_tzc_regions_info_t;
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/*******************************************************************************
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* Default mapping definition of the TrustZone Controller for ARM standard
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* platforms.
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* Configure:
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* - Region 0 with no access;
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* - Region 1 with secure access only;
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* - the remaining DRAM regions access from the given Non-Secure masters.
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******************************************************************************/
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#if ENABLE_SPM && SPM_MM
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#define ARM_TZC_REGIONS_DEF \
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{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
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TZC_REGION_S_RDWR, 0}, \
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{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}
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#else
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#define ARM_TZC_REGIONS_DEF \
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{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
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TZC_REGION_S_RDWR, 0}, \
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{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}
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#endif
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#define ARM_CASSERT_MMAP \
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CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
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assert_plat_arm_mmap_mismatch); \
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CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
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<= MAX_MMAP_REGIONS, \
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assert_max_mmap_regions);
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void arm_setup_romlib(void);
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#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
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/*
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* Use this macro to instantiate lock before it is used in below
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* arm_lock_xxx() macros
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*/
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#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
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#define ARM_LOCK_GET_INSTANCE (&arm_lock)
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#if !HW_ASSISTED_COHERENCY
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#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
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#else
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#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
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#endif
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#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
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/*
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* These are wrapper macros to the Coherent Memory Bakery Lock API.
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*/
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#define arm_lock_init() bakery_lock_init(&arm_lock)
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#define arm_lock_get() bakery_lock_get(&arm_lock)
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#define arm_lock_release() bakery_lock_release(&arm_lock)
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#else
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/*
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* Empty macros for all other BL stages other than BL31 and BL32
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*/
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#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
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#define ARM_LOCK_GET_INSTANCE 0
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#define arm_lock_init()
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#define arm_lock_get()
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#define arm_lock_release()
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#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
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#if ARM_RECOM_STATE_ID_ENC
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define ARM_LOCAL_PSTATE_WIDTH 4
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#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
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/* Macros to construct the composite power state */
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/* Make composite power state parameter till power level 0 */
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#if PSCI_EXTENDED_STATE_ID
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#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
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#else
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#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#endif /* __PSCI_EXTENDED_STATE_ID__ */
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/* Make composite power state parameter till power level 1 */
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#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
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arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/* Make composite power state parameter till power level 2 */
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#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
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arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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/* ARM State switch error codes */
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#define STATE_SW_E_PARAM (-2)
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#define STATE_SW_E_DENIED (-3)
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/* IO storage utility functions */
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void arm_io_setup(void);
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/* Security utility functions */
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void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions);
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struct tzc_dmc500_driver_data;
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void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
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const arm_tzc_regions_info_t *tzc_regions);
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/* Console utility functions */
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void arm_console_boot_init(void);
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void arm_console_boot_end(void);
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void arm_console_runtime_init(void);
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void arm_console_runtime_end(void);
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/* Systimer utility function */
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void arm_configure_sys_timer(void);
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/* PM utility functions */
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int arm_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state);
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int arm_validate_psci_entrypoint(uintptr_t entrypoint);
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int arm_validate_ns_entrypoint(uintptr_t entrypoint);
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void arm_system_pwr_domain_save(void);
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void arm_system_pwr_domain_resume(void);
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int arm_psci_read_mem_protect(int *enabled);
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int arm_nor_psci_write_mem_protect(int val);
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void arm_nor_psci_do_static_mem_protect(void);
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void arm_nor_psci_do_dyn_mem_protect(void);
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int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
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/* Topology utility function */
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int arm_check_mpidr(u_register_t mpidr);
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/* BL1 utility functions */
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void arm_bl1_early_platform_setup(void);
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void arm_bl1_platform_setup(void);
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void arm_bl1_plat_arch_setup(void);
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/* BL2 utility functions */
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void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout);
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void arm_bl2_platform_setup(void);
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void arm_bl2_plat_arch_setup(void);
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uint32_t arm_get_spsr_for_bl32_entry(void);
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uint32_t arm_get_spsr_for_bl33_entry(void);
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int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
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int arm_bl2_handle_post_image_load(unsigned int image_id);
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struct bl_params *arm_get_next_bl_params(void);
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/* BL2 at EL3 functions */
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void arm_bl2_el3_early_platform_setup(void);
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void arm_bl2_el3_plat_arch_setup(void);
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/* BL2U utility functions */
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void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
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void *plat_info);
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void arm_bl2u_platform_setup(void);
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void arm_bl2u_plat_arch_setup(void);
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/* BL31 utility functions */
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void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
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uintptr_t hw_config, void *plat_params_from_bl2);
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void arm_bl31_platform_setup(void);
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void arm_bl31_plat_runtime_setup(void);
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void arm_bl31_plat_arch_setup(void);
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/* TSP utility functions */
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void arm_tsp_early_platform_setup(void);
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/* SP_MIN utility functions */
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void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
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uintptr_t hw_config, void *plat_params_from_bl2);
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void arm_sp_min_plat_runtime_setup(void);
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/* FIP TOC validity check */
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int arm_io_is_toc_valid(void);
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/* Utility functions for Dynamic Config */
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void arm_load_tb_fw_config(void);
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void arm_bl2_set_tb_cfg_addr(void *dtb);
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void arm_bl2_dyn_cfg_init(void);
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void arm_bl1_set_mbedtls_heap(void);
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int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
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/*
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* Free the memory storing initialization code only used during an images boot
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* time so it can be reclaimed for runtime data
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*/
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void arm_free_init_memory(void);
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/*
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* Mandatory functions required in ARM standard platforms
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*/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
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void plat_arm_gic_driver_init(void);
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void plat_arm_gic_init(void);
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void plat_arm_gic_cpuif_enable(void);
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void plat_arm_gic_cpuif_disable(void);
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void plat_arm_gic_redistif_on(void);
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void plat_arm_gic_redistif_off(void);
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void plat_arm_gic_pcpu_init(void);
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void plat_arm_gic_save(void);
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void plat_arm_gic_resume(void);
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void plat_arm_security_setup(void);
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void plat_arm_pwrc_setup(void);
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void plat_arm_interconnect_init(void);
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void plat_arm_interconnect_enter_coherency(void);
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void plat_arm_interconnect_exit_coherency(void);
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void plat_arm_program_trusted_mailbox(uintptr_t address);
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int plat_arm_bl1_fwu_needed(void);
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__dead2 void plat_arm_error_handler(int err);
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#if ARM_PLAT_MT
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unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
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#endif
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/*
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* This function is called after loading SCP_BL2 image and it is used to perform
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* any platform-specific actions required to handle the SCP firmware.
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*/
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int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
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/*
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* Optional functions required in ARM standard platforms
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*/
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void plat_arm_io_setup(void);
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int plat_arm_get_alt_image_source(
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unsigned int image_id,
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uintptr_t *dev_handle,
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uintptr_t *image_spec);
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unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
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const mmap_region_t *plat_arm_get_mmap(void);
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/* Allow platform to override psci_pm_ops during runtime */
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
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/* Execution state switch in ARM platforms */
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int arm_execution_state_switch(unsigned int smc_fid,
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uint32_t pc_hi,
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uint32_t pc_lo,
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uint32_t cookie_hi,
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uint32_t cookie_lo,
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void *handle);
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/* Optional functions for SP_MIN */
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void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3);
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/* global variables */
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extern plat_psci_ops_t plat_arm_psci_pm_ops;
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extern const mmap_region_t plat_arm_mmap[];
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extern const unsigned int arm_pm_idle_states[];
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/* secure watchdog */
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void plat_arm_secure_wdt_start(void);
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void plat_arm_secure_wdt_stop(void);
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#endif /* PLAT_ARM_H */
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