45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DENVER_H
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#define DENVER_H
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/* MIDR values for Denver */
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#define DENVER_MIDR_PN0 U(0x4E0F0000)
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#define DENVER_MIDR_PN1 U(0x4E0F0010)
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#define DENVER_MIDR_PN2 U(0x4E0F0020)
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#define DENVER_MIDR_PN3 U(0x4E0F0030)
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#define DENVER_MIDR_PN4 U(0x4E0F0040)
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/* Implementer code in the MIDR register */
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#define DENVER_IMPL U(0x4E)
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/* CPU state ids - implementation defined */
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#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
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/* Speculative store buffering */
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#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11)
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#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18)
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/* Speculative memory disambiguation */
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#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9)
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#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17)
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/* Core power management states */
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#define DENVER_CPU_PMSTATE_C1 U(0x1)
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#define DENVER_CPU_PMSTATE_C6 U(0x6)
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#define DENVER_CPU_PMSTATE_C7 U(0x7)
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#define DENVER_CPU_PMSTATE_MASK U(0xF)
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#ifndef __ASSEMBLER__
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/* Disable Dynamic Code Optimisation */
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void denver_disable_dco(void);
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#endif /* __ASSEMBLER__ */
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#endif /* DENVER_H */
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