220 lines
5.5 KiB
ArmAsm
220 lines
5.5 KiB
ArmAsm
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ASM_MACROS_S
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#define ASM_MACROS_S
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#include <arch.h>
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#include <common/asm_macros_common.S>
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#include <lib/spinlock.h>
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/*
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* TLBI instruction with type specifier that implements the workaround for
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* errata 813419 of Cortex-A57.
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*/
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#if ERRATA_A57_813419
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#define TLB_INVALIDATE(_reg, _coproc) \
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stcopr _reg, _coproc; \
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dsb ish; \
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stcopr _reg, _coproc
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#else
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#define TLB_INVALIDATE(_reg, _coproc) \
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stcopr _reg, _coproc
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#endif
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#define WORD_SIZE 4
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/*
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* Co processor register accessors
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*/
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.macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
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mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
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.endm
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.macro ldcopr16 reg1, reg2, coproc, opc1, CRm
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mrrc \coproc, \opc1, \reg1, \reg2, \CRm
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.endm
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.macro stcopr reg, coproc, opc1, CRn, CRm, opc2
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mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
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.endm
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.macro stcopr16 reg1, reg2, coproc, opc1, CRm
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mcrr \coproc, \opc1, \reg1, \reg2, \CRm
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.endm
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/* Cache line size helpers */
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.macro dcache_line_size reg, tmp
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ldcopr \tmp, CTR
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ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH
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mov \reg, #WORD_SIZE
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lsl \reg, \reg, \tmp
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.endm
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.macro icache_line_size reg, tmp
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ldcopr \tmp, CTR
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and \tmp, \tmp, #CTR_IMINLINE_MASK
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mov \reg, #WORD_SIZE
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lsl \reg, \reg, \tmp
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.endm
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 32 byte boundary.
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*/
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.macro vector_base label
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.section .vectors, "ax"
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.align 5
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\label:
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.endm
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/*
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* This macro calculates the base address of the current CPU's multi
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* processor(MP) stack using the plat_my_core_pos() index, the name of
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* the stack storage and the size of each stack.
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* Out: r0 = physical address of stack base
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* Clobber: r14, r1, r2
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*/
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.macro get_my_mp_stack _name, _size
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bl plat_my_core_pos
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ldr r2, =(\_name + \_size)
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mov r1, #\_size
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mla r0, r0, r1, r2
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.endm
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/*
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* This macro calculates the base address of a uniprocessor(UP) stack
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* using the name of the stack storage and the size of the stack
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* Out: r0 = physical address of stack base
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*/
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.macro get_up_stack _name, _size
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ldr r0, =(\_name + \_size)
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.endm
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#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
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/*
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* ARMv7 cores without Virtualization extension do not support the
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* eret instruction.
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*/
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.macro eret
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movs pc, lr
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.endm
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#endif
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#if (ARM_ARCH_MAJOR == 7)
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/* ARMv7 does not support stl instruction */
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.macro stl _reg, _write_lock
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dmb
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str \_reg, \_write_lock
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dsb
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.endm
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#endif
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/*
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* Helper macro to generate the best mov/movw/movt combinations
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* according to the value to be moved.
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*/
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.macro mov_imm _reg, _val
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.if ((\_val) & 0xffff0000) == 0
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mov \_reg, #(\_val)
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.else
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movw \_reg, #((\_val) & 0xffff)
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movt \_reg, #((\_val) >> 16)
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.endif
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.endm
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/*
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* Macro to mark instances where we're jumping to a function and don't
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* expect a return. To provide the function being jumped to with
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* additional information, we use 'bl' instruction to jump rather than
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* 'b'.
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*
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* Debuggers infer the location of a call from where LR points to, which
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* is usually the instruction after 'bl'. If this macro expansion
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* happens to be the last location in a function, that'll cause the LR
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* to point a location beyond the function, thereby misleading debugger
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* back trace. We therefore insert a 'nop' after the function call for
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* debug builds, unless 'skip_nop' parameter is non-zero.
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*/
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.macro no_ret _func:req, skip_nop=0
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bl \_func
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#if DEBUG
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.ifeq \skip_nop
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nop
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.endif
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#endif
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.endm
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/*
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* Reserve space for a spin lock in assembly file.
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*/
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.macro define_asm_spinlock _name:req
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.align SPINLOCK_ASM_ALIGN
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\_name:
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.space SPINLOCK_ASM_SIZE
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.endm
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/*
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* Helper macro to OR the bottom 32 bits of `_val` into `_reg_l`
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* and the top 32 bits of `_val` into `_reg_h`. If either the bottom
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* or top word of `_val` is zero, the corresponding OR operation
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* is skipped.
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*/
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.macro orr64_imm _reg_l, _reg_h, _val
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.if (\_val >> 32)
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orr \_reg_h, \_reg_h, #(\_val >> 32)
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.endif
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.if (\_val & 0xffffffff)
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orr \_reg_l, \_reg_l, #(\_val & 0xffffffff)
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.endif
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.endm
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/*
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* Helper macro to bitwise-clear bits in `_reg_l` and
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* `_reg_h` given a 64 bit immediate `_val`. The set bits
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* in the bottom word of `_val` dictate which bits from
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* `_reg_l` should be cleared. Similarly, the set bits in
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* the top word of `_val` dictate which bits from `_reg_h`
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* should be cleared. If either the bottom or top word of
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* `_val` is zero, the corresponding BIC operation is skipped.
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*/
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.macro bic64_imm _reg_l, _reg_h, _val
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.if (\_val >> 32)
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bic \_reg_h, \_reg_h, #(\_val >> 32)
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.endif
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.if (\_val & 0xffffffff)
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bic \_reg_l, \_reg_l, #(\_val & 0xffffffff)
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.endif
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.endm
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/*
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* Helper macro for carrying out division in software when
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* hardware division is not suported. \top holds the dividend
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* in the function call and the remainder after
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* the function is executed. \bot holds the divisor. \div holds
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* the quotient and \temp is a temporary registed used in calcualtion.
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* The division algorithm has been obtained from:
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* http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm
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*/
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.macro softudiv div:req,top:req,bot:req,temp:req
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mov \temp, \bot
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cmp \temp, \top, lsr #1
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div1:
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movls \temp, \temp, lsl #1
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cmp \temp, \top, lsr #1
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bls div1
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mov \div, #0
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div2:
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cmp \top, \temp
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subcs \top, \top,\temp
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ADC \div, \div, \div
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mov \temp, \temp, lsr #1
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cmp \temp, \bot
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bhs div2
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.endm
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#endif /* ASM_MACROS_S */
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