57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include "plat_ls.h"
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#include "fsl_csu.h"
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/* slave interfaces according to the RM */
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static const int cci_map[] = {
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4,
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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#ifdef LS_BL2_IN_OCRAM
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unsigned long romem_base = (unsigned long)(&__TEXT_START__);
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unsigned long romem_size = (unsigned long)(&__RODATA_END__)
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- romem_base;
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/* Check the Text and RO-Data region size */
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if (romem_size > BL31_TEXT_RODATA_SIZE) {
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ERROR("BL31 Text and RO-Data region size exceed reserved memory size\n");
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panic();
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}
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#endif
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/*
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* Initialize system level generic timer for Layerscape Socs.
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*/
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ls_delay_timer_init();
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ls_bl31_early_platform_setup((void *)arg0, (void *)arg3);
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/*
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* Initialize the correct interconnect for this cluster during cold
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* boot. No need for locks as no other CPU is active.
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*/
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cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
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/*
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* Enable coherency in interconnect for the primary CPU's cluster.
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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*/
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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/* Init CSU to enable non-secure access to peripherals */
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enable_layerscape_ns_access();
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}
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