144 lines
4.6 KiB
C
144 lines
4.6 KiB
C
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_SPM_DEF_H
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#define ARM_SPM_DEF_H
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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/*
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* Reserve 4 MiB for binaries of Secure Partitions and Resource Description
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* blobs.
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*/
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#define PLAT_SP_PACKAGE_BASE BL32_BASE
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#define PLAT_SP_PACKAGE_SIZE ULL(0x400000)
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#define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \
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PLAT_SP_PACKAGE_BASE, \
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PLAT_SP_PACKAGE_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \
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PLAT_SP_PACKAGE_BASE, \
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PLAT_SP_PACKAGE_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* The rest of the memory reserved for BL32 is free for SPM to use it as memory
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* pool to allocate memory regions requested in the resource description.
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*/
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#define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE)
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#define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE)
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#if SPM_MM
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/*
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* If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
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* region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
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* at the base of DRAM.
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*/
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#define ARM_SP_IMAGE_BASE BL32_BASE
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#define ARM_SP_IMAGE_LIMIT BL32_LIMIT
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/* The maximum size of the S-EL0 payload can be 3MB */
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#define ARM_SP_IMAGE_SIZE ULL(0x300000)
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#ifdef IMAGE_BL2
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/* SPM Payload memory. Mapped as RW in BL2. */
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#define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#ifdef IMAGE_BL31
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/* SPM Payload memory. Mapped as code in S-EL1 */
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#define ARM_SP_IMAGE_MMAP MAP_REGION2( \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_SIZE, \
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MT_CODE | MT_SECURE | MT_USER, \
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PAGE_SIZE)
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#endif
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/*
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* Memory shared between EL3 and S-EL0. It is used by EL3 to push data into
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* S-EL0, so it is mapped with RW permission from EL3 and with RO permission
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* from S-EL0. Placed after SPM Payload memory.
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*/
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#define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE)
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#define PLAT_SPM_BUF_SIZE ULL(0x100000)
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#define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RW_DATA | MT_SECURE)
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#define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RO_DATA | MT_SECURE | MT_USER,\
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PAGE_SIZE)
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/*
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* Memory shared between Normal world and S-EL0 for passing data during service
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* requests. Mapped as RW and NS. Placed after the shared memory between EL3 and
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* S-EL0.
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*/
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#define PLAT_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
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#define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
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#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
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PLAT_SP_IMAGE_NS_BUF_BASE, \
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PLAT_SP_IMAGE_NS_BUF_BASE, \
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PLAT_SP_IMAGE_NS_BUF_SIZE, \
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MT_RW_DATA | MT_NS | MT_USER, \
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PAGE_SIZE)
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/*
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* RW memory, which uses the remaining Trusted DRAM. Placed after the memory
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* shared between Secure and Non-secure worlds, or after the platform specific
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* buffers, if defined. First there is the stack memory for all CPUs and then
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* there is the common heap memory. Both are mapped with RW permissions.
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*/
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#define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
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#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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#define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \
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ARM_SP_IMAGE_STACK_TOTAL_SIZE)
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#define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE)
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#define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \
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PLAT_SP_IMAGE_STACK_BASE, \
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PLAT_SP_IMAGE_STACK_BASE, \
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(ARM_SP_IMAGE_LIMIT - \
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PLAT_SP_IMAGE_STACK_BASE), \
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MT_RW_DATA | MT_SECURE | MT_USER,\
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PAGE_SIZE)
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/* Total number of memory regions with distinct properties */
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#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
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#endif /* SPM_MM */
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/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
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#define PLAT_SPM_COOKIE_0 ULL(0)
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#define PLAT_SPM_COOKIE_1 ULL(0)
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/*
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* Max number of elements supported by SPM in this platform. The defines below
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* are used to allocate memory at compile time for different arrays in SPM.
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*/
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#define PLAT_SPM_MAX_PARTITIONS U(2)
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#define PLAT_SPM_MEM_REGIONS_MAX U(80)
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#define PLAT_SPM_NOTIFICATIONS_MAX U(30)
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#define PLAT_SPM_SERVICES_MAX U(30)
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#define PLAT_SPCI_HANDLES_MAX_NUM U(20)
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#define PLAT_SPM_RESPONSES_MAX U(30)
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#endif /* ARM_SPM_DEF_H */
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