164 lines
6.4 KiB
JSON
164 lines
6.4 KiB
JSON
[
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{
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"EventCode": "0x28",
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"UMask": "0x7",
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
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"Counter": "0,1,2,3",
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"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
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"PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
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"SampleAfterValue": "200003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x28",
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"UMask": "0x18",
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
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"Counter": "0,1,2,3",
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"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
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"PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
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"SampleAfterValue": "200003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x28",
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"UMask": "0x20",
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
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"Counter": "0,1,2,3",
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"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
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"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
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"SampleAfterValue": "200003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x28",
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"UMask": "0x40",
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"BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
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"Counter": "0,1,2,3",
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"EventName": "CORE_POWER.THROTTLE",
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"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
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"SampleAfterValue": "200003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x32",
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"UMask": "0x1",
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"BriefDescription": "Number of PREFETCHNTA instructions executed.",
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"Counter": "0,1,2,3",
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"EventName": "SW_PREFETCH_ACCESS.NTA",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x32",
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"UMask": "0x2",
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"BriefDescription": "Number of PREFETCHT0 instructions executed.",
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"Counter": "0,1,2,3",
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"EventName": "SW_PREFETCH_ACCESS.T0",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x32",
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"UMask": "0x4",
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"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
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"Counter": "0,1,2,3",
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"EventName": "SW_PREFETCH_ACCESS.T1_T2",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x32",
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"UMask": "0x8",
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"BriefDescription": "Number of PREFETCHW instructions executed.",
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"Counter": "0,1,2,3",
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"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xCB",
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"UMask": "0x1",
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"BriefDescription": "Number of hardware interrupts received by the processor.",
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"Counter": "0,1,2,3",
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"EventName": "HW_INTERRUPTS.RECEIVED",
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"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
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"SampleAfterValue": "203",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x1",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x2",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x4",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x8",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x10",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x20",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xEF",
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"UMask": "0x40",
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"Counter": "0,1,2,3",
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"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xFE",
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"UMask": "0x2",
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"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
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"Counter": "0,1,2,3",
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"EventName": "IDI_MISC.WB_UPGRADE",
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"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xFE",
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"UMask": "0x4",
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"BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
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"Counter": "0,1,2,3",
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"EventName": "IDI_MISC.WB_DOWNGRADE",
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"PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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] |