163 lines
6.0 KiB
JSON
163 lines
6.0 KiB
JSON
[
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{
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"EventName": "ls_locks.bus_lock",
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"EventCode": "0x25",
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"BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
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"PublicDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
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"UMask": "0x1"
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},
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{
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"EventName": "ls_dispatch.ld_st_dispatch",
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"EventCode": "0x29",
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"BriefDescription": "Load-op-Stores.",
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"PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
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"UMask": "0x4"
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},
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{
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"EventName": "ls_dispatch.store_dispatch",
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"EventCode": "0x29",
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"BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
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"PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
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"UMask": "0x2"
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},
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{
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"EventName": "ls_dispatch.ld_dispatch",
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"EventCode": "0x29",
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"BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
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"PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
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"UMask": "0x1"
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},
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{
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"EventName": "ls_stlf",
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"EventCode": "0x35",
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"BriefDescription": "Number of STLF hits."
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},
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{
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"EventName": "ls_dc_accesses",
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"EventCode": "0x40",
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"BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
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},
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{
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"EventName": "ls_l1_d_tlb_miss.all",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Miss or Reload off all sizes.",
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"PublicDescription": "L1 DTLB Miss or Reload off all sizes.",
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"UMask": "0xff"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Miss of a page of 1G size.",
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"PublicDescription": "L1 DTLB Miss of a page of 1G size.",
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"UMask": "0x80"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Miss of a page of 2M size.",
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"PublicDescription": "L1 DTLB Miss of a page of 2M size.",
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"UMask": "0x40"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Miss of a page of 32K size.",
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"PublicDescription": "L1 DTLB Miss of a page of 32K size.",
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"UMask": "0x20"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Miss of a page of 4K size.",
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"PublicDescription": "L1 DTLB Miss of a page of 4K size.",
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"UMask": "0x10"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Reload of a page of 1G size.",
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"PublicDescription": "L1 DTLB Reload of a page of 1G size.",
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"UMask": "0x8"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Reload of a page of 2M size.",
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"PublicDescription": "L1 DTLB Reload of a page of 2M size.",
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"UMask": "0x4"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Reload of a page of 32K size.",
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"PublicDescription": "L1 DTLB Reload of a page of 32K size.",
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"UMask": "0x2"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Reload of a page of 4K size.",
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"PublicDescription": "L1 DTLB Reload of a page of 4K size.",
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"UMask": "0x1"
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},
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{
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"EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_iside",
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"EventCode": "0x46",
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"BriefDescription": "Tablewalker allocation.",
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"PublicDescription": "Tablewalker allocation.",
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"UMask": "0xc"
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},
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{
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"EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_dside",
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"EventCode": "0x46",
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"BriefDescription": "Tablewalker allocation.",
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"PublicDescription": "Tablewalker allocation.",
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"UMask": "0x3"
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},
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{
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"EventName": "ls_misal_accesses",
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"EventCode": "0x47",
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"BriefDescription": "Misaligned loads."
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},
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{
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"EventName": "ls_pref_instr_disp.prefetch_nta",
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"EventCode": "0x4b",
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"BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
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"PublicDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
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"UMask": "0x4"
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},
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{
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"EventName": "ls_pref_instr_disp.store_prefetch_w",
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"EventCode": "0x4b",
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"BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
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"PublicDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
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"UMask": "0x2"
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},
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{
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"EventName": "ls_pref_instr_disp.load_prefetch_w",
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"EventCode": "0x4b",
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"BriefDescription": "Prefetch, Prefetch_T0_T1_T2.",
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"PublicDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.",
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"UMask": "0x1"
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},
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{
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"EventName": "ls_inef_sw_pref.mab_mch_cnt",
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"EventCode": "0x52",
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"BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
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"PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
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"UMask": "0x2"
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},
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{
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"EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
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"EventCode": "0x52",
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"BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
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"PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
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"UMask": "0x1"
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},
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{
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"EventName": "ls_not_halted_cyc",
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"EventCode": "0x76",
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"BriefDescription": "Cycles not in Halt."
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}
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]
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