609 lines
19 KiB
C
609 lines
19 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2017 Intel Corporation. All rights reserved.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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#ifndef __SOF_INTEL_HDA_H
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#define __SOF_INTEL_HDA_H
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#include <sound/hda_codec.h>
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#include <sound/hdaudio_ext.h>
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#include "shim.h"
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/* PCI registers */
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#define PCI_TCSEL 0x44
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#define PCI_PGCTL PCI_TCSEL
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#define PCI_CGCTL 0x48
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/* PCI_PGCTL bits */
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#define PCI_PGCTL_ADSPPGD BIT(2)
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#define PCI_PGCTL_LSRMD_MASK BIT(4)
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/* PCI_CGCTL bits */
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#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
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#define PCI_CGCTL_ADSPDCGE BIT(1)
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/* Legacy HDA registers and bits used - widths are variable */
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#define SOF_HDA_GCAP 0x0
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#define SOF_HDA_GCTL 0x8
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/* accept unsol. response enable */
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#define SOF_HDA_GCTL_UNSOL BIT(8)
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#define SOF_HDA_LLCH 0x14
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#define SOF_HDA_INTCTL 0x20
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#define SOF_HDA_INTSTS 0x24
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#define SOF_HDA_WAKESTS 0x0E
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#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
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#define SOF_HDA_RIRBSTS 0x5d
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/* SOF_HDA_GCTL register bist */
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#define SOF_HDA_GCTL_RESET BIT(0)
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/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
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#define SOF_HDA_INT_GLOBAL_EN BIT(31)
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#define SOF_HDA_INT_CTRL_EN BIT(30)
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#define SOF_HDA_INT_ALL_STREAM 0xff
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#define SOF_HDA_MAX_CAPS 10
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#define SOF_HDA_CAP_ID_OFF 16
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#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
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SOF_HDA_CAP_ID_OFF)
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#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
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#define SOF_HDA_GTS_CAP_ID 0x1
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#define SOF_HDA_ML_CAP_ID 0x2
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#define SOF_HDA_PP_CAP_ID 0x3
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#define SOF_HDA_REG_PP_PPCH 0x10
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#define SOF_HDA_REG_PP_PPCTL 0x04
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#define SOF_HDA_REG_PP_PPSTS 0x08
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#define SOF_HDA_PPCTL_PIE BIT(31)
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#define SOF_HDA_PPCTL_GPROCEN BIT(30)
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/* DPIB entry size: 8 Bytes = 2 DWords */
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#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
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#define SOF_HDA_SPIB_CAP_ID 0x4
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#define SOF_HDA_DRSM_CAP_ID 0x5
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#define SOF_HDA_SPIB_BASE 0x08
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#define SOF_HDA_SPIB_INTERVAL 0x08
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#define SOF_HDA_SPIB_SPIB 0x00
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#define SOF_HDA_SPIB_MAXFIFO 0x04
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#define SOF_HDA_PPHC_BASE 0x10
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#define SOF_HDA_PPHC_INTERVAL 0x10
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#define SOF_HDA_PPLC_BASE 0x10
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#define SOF_HDA_PPLC_MULTI 0x10
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#define SOF_HDA_PPLC_INTERVAL 0x10
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#define SOF_HDA_DRSM_BASE 0x08
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#define SOF_HDA_DRSM_INTERVAL 0x08
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/* Descriptor error interrupt */
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#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
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/* FIFO error interrupt */
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#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
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/* Buffer completion interrupt */
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#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
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#define SOF_HDA_CL_DMA_SD_INT_MASK \
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(SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
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SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
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SOF_HDA_CL_DMA_SD_INT_COMPLETE)
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#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
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/* Intel HD Audio Code Loader DMA Registers */
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#define SOF_HDA_ADSP_LOADER_BASE 0x80
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#define SOF_HDA_ADSP_DPLBASE 0x70
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#define SOF_HDA_ADSP_DPUBASE 0x74
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#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
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/* Stream Registers */
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#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
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#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
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#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
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#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
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#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
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#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
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#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
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#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
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#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
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#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
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#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
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#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
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/* CL: Software Position Based FIFO Capability Registers */
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#define SOF_DSP_REG_CL_SPBFIFO \
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(SOF_HDA_ADSP_LOADER_BASE + 0x20)
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#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
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#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
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#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
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#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
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/* Stream Number */
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#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
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#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
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GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
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SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
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#define HDA_DSP_HDA_BAR 0
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#define HDA_DSP_PP_BAR 1
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#define HDA_DSP_SPIB_BAR 2
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#define HDA_DSP_DRSM_BAR 3
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#define HDA_DSP_BAR 4
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#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
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#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
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#define HDA_DSP_PANIC_OFFSET(x) \
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(((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
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/* SRAM window 0 FW "registers" */
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#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
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#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
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/* FW and ROM share offset 4 */
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#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
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#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
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#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
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#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
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#define HDA_DSP_STREAM_RESET_TIMEOUT 300
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/*
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* Timeout in us, for setting the stream RUN bit, during
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* start/stop the stream. The timeout expires if new RUN bit
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* value cannot be read back within the specified time.
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*/
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#define HDA_DSP_STREAM_RUN_TIMEOUT 300
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#define HDA_DSP_CL_TRIGGER_TIMEOUT 300
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#define HDA_DSP_SPIB_ENABLE 1
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#define HDA_DSP_SPIB_DISABLE 0
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#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
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#define HDA_DSP_STACK_DUMP_SIZE 32
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/* ROM status/error values */
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#define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
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#define HDA_DSP_ROM_INIT 0x1
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#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
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#define HDA_DSP_ROM_FW_FW_LOADED 0x4
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#define HDA_DSP_ROM_FW_ENTERED 0x5
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#define HDA_DSP_ROM_RFW_START 0xf
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#define HDA_DSP_ROM_CSE_ERROR 40
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#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
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#define HDA_DSP_ROM_IMR_TO_SMALL 42
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#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
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#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
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#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
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#define HDA_DSP_ROM_L2_CACHE_ERROR 46
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#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
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#define HDA_DSP_ROM_API_PTR_INVALID 50
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#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
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#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
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#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
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#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
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#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
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#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
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#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
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#define HDA_DSP_IPC_PURGE_FW 0x01004000
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/* various timeout values */
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#define HDA_DSP_PU_TIMEOUT 50
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#define HDA_DSP_PD_TIMEOUT 50
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#define HDA_DSP_RESET_TIMEOUT_US 50000
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#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
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#define HDA_DSP_INIT_TIMEOUT_US 500000
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#define HDA_DSP_CTRL_RESET_TIMEOUT 100
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#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
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#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
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#define HDA_DSP_ADSPIC_IPC 1
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#define HDA_DSP_ADSPIS_IPC 1
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/* Intel HD Audio General DSP Registers */
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#define HDA_DSP_GEN_BASE 0x0
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#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
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#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
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#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
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#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
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#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
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/* Intel HD Audio Inter-Processor Communication Registers */
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#define HDA_DSP_IPC_BASE 0x40
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#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
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#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
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#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
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#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
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#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
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/* Intel Vendor Specific Registers */
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#define HDA_VS_INTEL_EM2 0x1030
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#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
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/* HIPCI */
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#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
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#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
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/* HIPCIE */
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#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
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#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
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/* HIPCCTL */
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#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
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#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
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/* HIPCT */
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#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
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#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
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/* HIPCTE */
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#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
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#define HDA_DSP_ADSPIC_CL_DMA 0x2
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#define HDA_DSP_ADSPIS_CL_DMA 0x2
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/* Delay before scheduling D0i3 entry */
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#define BXT_D0I3_DELAY 5000
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#define FW_CL_STREAM_NUMBER 0x1
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/* ADSPCS - Audio DSP Control & Status */
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/*
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* Core Reset - asserted high
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* CRST Mask for a given core mask pattern, cm
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*/
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#define HDA_DSP_ADSPCS_CRST_SHIFT 0
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#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
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/*
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* Core run/stall - when set to '1' core is stalled
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* CSTALL Mask for a given core mask pattern, cm
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*/
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#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
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#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
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/*
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* Set Power Active - when set to '1' turn cores on
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* SPA Mask for a given core mask pattern, cm
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*/
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#define HDA_DSP_ADSPCS_SPA_SHIFT 16
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#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
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/*
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* Current Power Active - power status of cores, set by hardware
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* CPA Mask for a given core mask pattern, cm
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*/
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#define HDA_DSP_ADSPCS_CPA_SHIFT 24
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#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
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/* Mask for a given core index, c = 0.. number of supported cores - 1 */
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#define HDA_DSP_CORE_MASK(c) BIT(c)
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/*
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* Mask for a given number of cores
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* nc = number of supported cores
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*/
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#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
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/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
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#define CNL_DSP_IPC_BASE 0xc0
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#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
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#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
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#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
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#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
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#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
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#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
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/* HIPCI */
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#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
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#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
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/* HIPCIE */
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#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
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#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
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/* HIPCCTL */
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#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
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#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
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/* HIPCT */
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#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
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#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
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/* HIPCTDA */
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#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
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#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
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/* HIPCTDD */
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#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
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/* BDL */
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#define HDA_DSP_BDL_SIZE 4096
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#define HDA_DSP_MAX_BDL_ENTRIES \
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(HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
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/* Number of DAIs */
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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#define SOF_SKL_NUM_DAIS 15
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#else
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#define SOF_SKL_NUM_DAIS 8
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#endif
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/* Intel HD Audio SRAM Window 0*/
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#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
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/* Firmware status window */
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#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
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#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
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/* Host Device Memory Space */
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#define APL_SSP_BASE_OFFSET 0x2000
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#define CNL_SSP_BASE_OFFSET 0x10000
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/* Host Device Memory Size of a Single SSP */
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#define SSP_DEV_MEM_SIZE 0x1000
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/* SSP Count of the Platform */
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#define APL_SSP_COUNT 6
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#define CNL_SSP_COUNT 3
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#define ICL_SSP_COUNT 6
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/* SSP Registers */
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#define SSP_SSC1_OFFSET 0x4
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#define SSP_SET_SCLK_SLAVE BIT(25)
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#define SSP_SET_SFRM_SLAVE BIT(24)
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#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
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#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
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struct sof_intel_dsp_bdl {
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__le32 addr_l;
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__le32 addr_h;
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__le32 size;
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__le32 ioc;
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} __attribute((packed));
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#define SOF_HDA_PLAYBACK_STREAMS 16
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#define SOF_HDA_CAPTURE_STREAMS 16
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#define SOF_HDA_PLAYBACK 0
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#define SOF_HDA_CAPTURE 1
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/* represents DSP HDA controller frontend - i.e. host facing control */
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struct sof_intel_hda_dev {
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struct hda_bus hbus;
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/* hw config */
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const struct sof_intel_dsp_desc *desc;
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/* trace */
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struct hdac_ext_stream *dtrace_stream;
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/* if position update IPC needed */
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u32 no_ipc_position;
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/* the maximum number of streams (playback + capture) supported */
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u32 stream_max;
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int irq;
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/* DMIC device */
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struct platform_device *dmic_dev;
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};
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static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
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{
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struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
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return &hda->hbus.core;
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}
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static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
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{
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struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
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return &hda->hbus;
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}
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struct sof_intel_hda_stream {
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struct snd_sof_dev *sdev;
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struct hdac_ext_stream hda_stream;
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struct sof_intel_stream stream;
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int host_reserved; /* reserve host DMA channel */
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};
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#define hstream_to_sof_hda_stream(hstream) \
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container_of(hstream, struct sof_intel_hda_stream, hda_stream)
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#define bus_to_sof_hda(bus) \
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container_of(bus, struct sof_intel_hda_dev, hbus.core)
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#define SOF_STREAM_SD_OFFSET(s) \
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(SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
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+ SOF_HDA_ADSP_LOADER_BASE)
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/*
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* DSP Core services.
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*/
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int hda_dsp_probe(struct snd_sof_dev *sdev);
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int hda_dsp_remove(struct snd_sof_dev *sdev);
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int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
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unsigned int core_mask);
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int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
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unsigned int core_mask);
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int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
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int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
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int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
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int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
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int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
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bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
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|
unsigned int core_mask);
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int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
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|
unsigned int core_mask);
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void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
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void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
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|
|
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int hda_dsp_suspend(struct snd_sof_dev *sdev);
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int hda_dsp_resume(struct snd_sof_dev *sdev);
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int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
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int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
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int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
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int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
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void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
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void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
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void hda_ipc_dump(struct snd_sof_dev *sdev);
|
|
void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
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|
|
|
/*
|
|
* DSP PCM Operations.
|
|
*/
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|
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
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|
struct snd_pcm_substream *substream);
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|
int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
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|
struct snd_pcm_substream *substream);
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|
int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
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|
struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct sof_ipc_stream_params *ipc_params);
|
|
int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream);
|
|
int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream, int cmd);
|
|
snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream);
|
|
|
|
/*
|
|
* DSP Stream Operations.
|
|
*/
|
|
|
|
int hda_dsp_stream_init(struct snd_sof_dev *sdev);
|
|
void hda_dsp_stream_free(struct snd_sof_dev *sdev);
|
|
int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
|
|
struct hdac_ext_stream *stream,
|
|
struct snd_dma_buffer *dmab,
|
|
struct snd_pcm_hw_params *params);
|
|
int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
|
|
struct hdac_ext_stream *stream, int cmd);
|
|
irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
|
|
irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
|
|
int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
|
|
struct snd_dma_buffer *dmab,
|
|
struct hdac_stream *stream);
|
|
|
|
struct hdac_ext_stream *
|
|
hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
|
|
int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
|
|
int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
|
|
struct hdac_ext_stream *stream,
|
|
int enable, u32 size);
|
|
|
|
void hda_ipc_msg_data(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream,
|
|
void *p, size_t sz);
|
|
int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream,
|
|
const struct sof_ipc_pcm_params_reply *reply);
|
|
|
|
/*
|
|
* DSP IPC Operations.
|
|
*/
|
|
int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
|
|
struct snd_sof_ipc_msg *msg);
|
|
void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
|
|
int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
|
|
int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
|
|
|
|
irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
|
|
irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
|
|
int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
|
|
|
|
/*
|
|
* DSP Code loader.
|
|
*/
|
|
int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
|
|
int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
|
|
|
|
/* pre and post fw run ops */
|
|
int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
|
|
int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
|
|
|
|
/*
|
|
* HDA Controller Operations.
|
|
*/
|
|
int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
|
|
void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
|
|
void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
|
|
int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
|
|
void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
|
|
int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
|
|
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
|
|
void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
|
|
/*
|
|
* HDA bus operations.
|
|
*/
|
|
void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
|
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
/*
|
|
* HDA Codec operations.
|
|
*/
|
|
int hda_codec_probe_bus(struct snd_sof_dev *sdev);
|
|
void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
|
|
void hda_codec_jack_check(struct snd_sof_dev *sdev);
|
|
|
|
#endif /* CONFIG_SND_SOC_SOF_HDA */
|
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
|
|
|
|
void hda_codec_i915_get(struct snd_sof_dev *sdev);
|
|
void hda_codec_i915_put(struct snd_sof_dev *sdev);
|
|
int hda_codec_i915_init(struct snd_sof_dev *sdev);
|
|
int hda_codec_i915_exit(struct snd_sof_dev *sdev);
|
|
|
|
#else
|
|
|
|
static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { }
|
|
static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { }
|
|
static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
|
|
static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
|
|
|
|
#endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */
|
|
|
|
/*
|
|
* Trace Control.
|
|
*/
|
|
int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
|
|
int hda_dsp_trace_release(struct snd_sof_dev *sdev);
|
|
int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
|
|
|
|
/* common dai driver */
|
|
extern struct snd_soc_dai_driver skl_dai[];
|
|
|
|
/*
|
|
* Platform Specific HW abstraction Ops.
|
|
*/
|
|
extern const struct snd_sof_dsp_ops sof_apl_ops;
|
|
extern const struct snd_sof_dsp_ops sof_cnl_ops;
|
|
extern const struct snd_sof_dsp_ops sof_skl_ops;
|
|
|
|
extern const struct sof_intel_dsp_desc apl_chip_info;
|
|
extern const struct sof_intel_dsp_desc cnl_chip_info;
|
|
extern const struct sof_intel_dsp_desc skl_chip_info;
|
|
extern const struct sof_intel_dsp_desc icl_chip_info;
|
|
extern const struct sof_intel_dsp_desc tgl_chip_info;
|
|
extern const struct sof_intel_dsp_desc ehl_chip_info;
|
|
|
|
#endif
|