286 lines
7.9 KiB
C
286 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* card driver for the Xonar DG/DGX
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*
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* Copyright (c) Clemens Ladisch <clemens@ladisch.de>
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* Copyright (c) Roman Volkov <v1ron@mail.ru>
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*/
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/*
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* Xonar DG/DGX
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* ------------
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*
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* CS4245 and CS4361 both will mute all outputs if any clock ratio
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* is invalid.
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*
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* CMI8788:
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*
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* SPI 0 -> CS4245
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*
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* Playback:
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* I²S 1 -> CS4245
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* I²S 2 -> CS4361 (center/LFE)
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* I²S 3 -> CS4361 (surround)
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* I²S 4 -> CS4361 (front)
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* Capture:
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* I²S ADC 1 <- CS4245
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*
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* GPIO 3 <- ?
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* GPIO 4 <- headphone detect
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* GPIO 5 -> enable ADC analog circuit for the left channel
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* GPIO 6 -> enable ADC analog circuit for the right channel
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* GPIO 7 -> switch green rear output jack between CS4245 and and the first
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* channel of CS4361 (mechanical relay)
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* GPIO 8 -> enable output to speakers
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*
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* CS4245:
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*
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* input 0 <- mic
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* input 1 <- aux
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* input 2 <- front mic
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* input 4 <- line
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* DAC out -> headphones
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* aux out -> front panel headphones
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <sound/control.h>
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#include <sound/core.h>
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#include <sound/info.h>
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#include <sound/pcm.h>
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#include <sound/tlv.h>
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#include "oxygen.h"
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#include "xonar_dg.h"
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#include "cs4245.h"
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int cs4245_write_spi(struct oxygen *chip, u8 reg)
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{
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struct dg *data = chip->model_data;
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unsigned int packet;
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packet = reg << 8;
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packet |= (CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 16;
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packet |= data->cs4245_shadow[reg];
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return oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
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OXYGEN_SPI_DATA_LENGTH_3 |
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OXYGEN_SPI_CLOCK_1280 |
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(0 << OXYGEN_SPI_CODEC_SHIFT) |
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OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
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packet);
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}
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int cs4245_read_spi(struct oxygen *chip, u8 addr)
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{
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struct dg *data = chip->model_data;
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int ret;
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ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
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OXYGEN_SPI_DATA_LENGTH_2 |
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OXYGEN_SPI_CEN_LATCH_CLOCK_HI |
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OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT),
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((CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 8) | addr);
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if (ret < 0)
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return ret;
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ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
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OXYGEN_SPI_DATA_LENGTH_2 |
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OXYGEN_SPI_CEN_LATCH_CLOCK_HI |
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OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT),
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(CS4245_SPI_ADDRESS | CS4245_SPI_READ) << 8);
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if (ret < 0)
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return ret;
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data->cs4245_shadow[addr] = oxygen_read8(chip, OXYGEN_SPI_DATA1);
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return 0;
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}
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int cs4245_shadow_control(struct oxygen *chip, enum cs4245_shadow_operation op)
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{
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struct dg *data = chip->model_data;
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unsigned char addr;
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int ret;
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for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++) {
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ret = (op == CS4245_SAVE_TO_SHADOW ?
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cs4245_read_spi(chip, addr) :
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cs4245_write_spi(chip, addr));
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static void cs4245_init(struct oxygen *chip)
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{
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struct dg *data = chip->model_data;
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/* save the initial state: codec version, registers */
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cs4245_shadow_control(chip, CS4245_SAVE_TO_SHADOW);
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/*
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* Power up the CODEC internals, enable soft ramp & zero cross, work in
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* async. mode, enable aux output from DAC. Invert DAC output as in the
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* Windows driver.
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*/
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data->cs4245_shadow[CS4245_POWER_CTRL] = 0;
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data->cs4245_shadow[CS4245_SIGNAL_SEL] =
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CS4245_A_OUT_SEL_DAC | CS4245_ASYNCH;
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data->cs4245_shadow[CS4245_DAC_CTRL_1] =
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CS4245_DAC_FM_SINGLE | CS4245_DAC_DIF_LJUST;
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data->cs4245_shadow[CS4245_DAC_CTRL_2] =
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CS4245_DAC_SOFT | CS4245_DAC_ZERO | CS4245_INVERT_DAC;
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data->cs4245_shadow[CS4245_ADC_CTRL] =
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CS4245_ADC_FM_SINGLE | CS4245_ADC_DIF_LJUST;
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data->cs4245_shadow[CS4245_ANALOG_IN] =
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CS4245_PGA_SOFT | CS4245_PGA_ZERO;
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data->cs4245_shadow[CS4245_PGA_B_CTRL] = 0;
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data->cs4245_shadow[CS4245_PGA_A_CTRL] = 0;
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data->cs4245_shadow[CS4245_DAC_A_CTRL] = 8;
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data->cs4245_shadow[CS4245_DAC_B_CTRL] = 8;
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cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
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snd_component_add(chip->card, "CS4245");
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}
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void dg_init(struct oxygen *chip)
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{
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struct dg *data = chip->model_data;
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data->output_sel = PLAYBACK_DST_HP_FP;
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data->input_sel = CAPTURE_SRC_MIC;
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cs4245_init(chip);
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oxygen_write16(chip, OXYGEN_GPIO_CONTROL,
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GPIO_OUTPUT_ENABLE | GPIO_HP_REAR | GPIO_INPUT_ROUTE);
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/* anti-pop delay, wait some time before enabling the output */
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msleep(2500);
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oxygen_write16(chip, OXYGEN_GPIO_DATA,
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GPIO_OUTPUT_ENABLE | GPIO_INPUT_ROUTE);
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}
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void dg_cleanup(struct oxygen *chip)
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{
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oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
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}
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void dg_suspend(struct oxygen *chip)
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{
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dg_cleanup(chip);
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}
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void dg_resume(struct oxygen *chip)
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{
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cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
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msleep(2500);
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oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
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}
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void set_cs4245_dac_params(struct oxygen *chip,
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struct snd_pcm_hw_params *params)
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{
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struct dg *data = chip->model_data;
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unsigned char dac_ctrl;
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unsigned char mclk_freq;
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dac_ctrl = data->cs4245_shadow[CS4245_DAC_CTRL_1] & ~CS4245_DAC_FM_MASK;
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mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK1_MASK;
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if (params_rate(params) <= 50000) {
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dac_ctrl |= CS4245_DAC_FM_SINGLE;
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mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
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} else if (params_rate(params) <= 100000) {
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dac_ctrl |= CS4245_DAC_FM_DOUBLE;
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mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
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} else {
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dac_ctrl |= CS4245_DAC_FM_QUAD;
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mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK1_SHIFT;
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}
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data->cs4245_shadow[CS4245_DAC_CTRL_1] = dac_ctrl;
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data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
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cs4245_write_spi(chip, CS4245_DAC_CTRL_1);
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cs4245_write_spi(chip, CS4245_MCLK_FREQ);
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}
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void set_cs4245_adc_params(struct oxygen *chip,
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struct snd_pcm_hw_params *params)
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{
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struct dg *data = chip->model_data;
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unsigned char adc_ctrl;
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unsigned char mclk_freq;
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adc_ctrl = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_ADC_FM_MASK;
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mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK2_MASK;
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if (params_rate(params) <= 50000) {
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adc_ctrl |= CS4245_ADC_FM_SINGLE;
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mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
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} else if (params_rate(params) <= 100000) {
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adc_ctrl |= CS4245_ADC_FM_DOUBLE;
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mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
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} else {
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adc_ctrl |= CS4245_ADC_FM_QUAD;
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mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK2_SHIFT;
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}
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data->cs4245_shadow[CS4245_ADC_CTRL] = adc_ctrl;
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data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
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cs4245_write_spi(chip, CS4245_ADC_CTRL);
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cs4245_write_spi(chip, CS4245_MCLK_FREQ);
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}
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static inline unsigned int shift_bits(unsigned int value,
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unsigned int shift_from,
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unsigned int shift_to,
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unsigned int mask)
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{
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if (shift_from < shift_to)
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return (value << (shift_to - shift_from)) & mask;
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else
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return (value >> (shift_from - shift_to)) & mask;
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}
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unsigned int adjust_dg_dac_routing(struct oxygen *chip,
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unsigned int play_routing)
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{
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struct dg *data = chip->model_data;
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switch (data->output_sel) {
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case PLAYBACK_DST_HP:
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case PLAYBACK_DST_HP_FP:
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oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
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OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 |
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OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE_MASK);
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break;
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case PLAYBACK_DST_MULTICH:
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oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
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OXYGEN_PLAY_MUTE01, OXYGEN_PLAY_MUTE_MASK);
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break;
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}
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return (play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) |
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shift_bits(play_routing,
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OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
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OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
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OXYGEN_PLAY_DAC1_SOURCE_MASK) |
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shift_bits(play_routing,
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OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
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OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
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OXYGEN_PLAY_DAC2_SOURCE_MASK) |
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shift_bits(play_routing,
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OXYGEN_PLAY_DAC0_SOURCE_SHIFT,
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OXYGEN_PLAY_DAC3_SOURCE_SHIFT,
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OXYGEN_PLAY_DAC3_SOURCE_MASK);
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}
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void dump_cs4245_registers(struct oxygen *chip,
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struct snd_info_buffer *buffer)
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{
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struct dg *data = chip->model_data;
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unsigned int addr;
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snd_iprintf(buffer, "\nCS4245:");
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cs4245_read_spi(chip, CS4245_INT_STATUS);
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for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++)
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snd_iprintf(buffer, " %02x", data->cs4245_shadow[addr]);
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snd_iprintf(buffer, "\n");
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}
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