655 lines
16 KiB
C
655 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 Impinj, Inc
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* Based on the code of analogus driver:
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*
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* Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/power/imx7-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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#define GPC_LPCR_A_CORE_BSC 0x000
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#define GPC_PGC_CPU_MAPPING 0x0ec
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#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
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#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
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#define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
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#define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3)
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#define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2)
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#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
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#define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
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#define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
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#define IMX8M_DISP_A53_DOMAIN BIT(12)
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#define IMX8M_HDMI_A53_DOMAIN BIT(11)
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#define IMX8M_VPU_A53_DOMAIN BIT(10)
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#define IMX8M_GPU_A53_DOMAIN BIT(9)
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#define IMX8M_DDR2_A53_DOMAIN BIT(8)
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#define IMX8M_DDR1_A53_DOMAIN BIT(7)
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#define IMX8M_OTG2_A53_DOMAIN BIT(5)
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#define IMX8M_OTG1_A53_DOMAIN BIT(4)
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#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
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#define IMX8M_MIPI_A53_DOMAIN BIT(2)
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
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#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
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#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
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#define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
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#define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
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#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
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#define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
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#define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
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#define IMX8M_DISP_SW_Pxx_REQ BIT(10)
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#define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
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#define IMX8M_VPU_SW_Pxx_REQ BIT(8)
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#define IMX8M_GPU_SW_Pxx_REQ BIT(7)
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#define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
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#define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
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#define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
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#define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
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#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
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#define GPC_M4_PU_PDN_FLG 0x1bc
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#define GPC_PU_PWRHSK 0x1fc
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#define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
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#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
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#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
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/*
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* The PGC offset values in Reference Manual
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* (Rev. 1, 01/2018 and the older ones) GPC chapter's
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* GPC_PGC memory map are incorrect, below offset
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* values are from design RTL.
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*/
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#define IMX7_PGC_MIPI 16
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#define IMX7_PGC_PCIE 17
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#define IMX7_PGC_USB_HSIC 20
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#define IMX8M_PGC_MIPI 16
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#define IMX8M_PGC_PCIE1 17
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#define IMX8M_PGC_OTG1 18
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#define IMX8M_PGC_OTG2 19
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#define IMX8M_PGC_DDR1 21
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#define IMX8M_PGC_GPU 23
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#define IMX8M_PGC_VPU 24
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#define IMX8M_PGC_DISP 26
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#define IMX8M_PGC_MIPI_CSI1 27
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#define IMX8M_PGC_MIPI_CSI2 28
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#define IMX8M_PGC_PCIE2 29
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#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
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#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
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#define GPC_PGC_CTRL_PCR BIT(0)
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#define GPC_CLK_MAX 6
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struct imx_pgc_domain {
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struct generic_pm_domain genpd;
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struct regmap *regmap;
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struct regulator *regulator;
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struct clk *clk[GPC_CLK_MAX];
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int num_clks;
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unsigned int pgc;
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const struct {
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u32 pxx;
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u32 map;
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u32 hsk;
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} bits;
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const int voltage;
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struct device *dev;
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};
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struct imx_pgc_domain_data {
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const struct imx_pgc_domain *domains;
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size_t domains_num;
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const struct regmap_access_table *reg_access_table;
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};
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static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
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bool on)
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{
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struct imx_pgc_domain *domain = container_of(genpd,
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struct imx_pgc_domain,
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genpd);
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unsigned int offset = on ?
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GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
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const bool enable_power_control = !on;
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const bool has_regulator = !IS_ERR(domain->regulator);
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int i, ret = 0;
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u32 pxx_req;
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regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
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domain->bits.map, domain->bits.map);
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if (has_regulator && on) {
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ret = regulator_enable(domain->regulator);
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if (ret) {
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dev_err(domain->dev, "failed to enable regulator\n");
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goto unmap;
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}
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}
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/* Enable reset clocks for all devices in the domain */
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for (i = 0; i < domain->num_clks; i++)
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clk_prepare_enable(domain->clk[i]);
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if (enable_power_control)
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regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
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GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
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if (domain->bits.hsk)
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regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
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domain->bits.hsk, on ? domain->bits.hsk : 0);
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regmap_update_bits(domain->regmap, offset,
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domain->bits.pxx, domain->bits.pxx);
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/*
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* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
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* for PUP_REQ/PDN_REQ bit to be cleared
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*/
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ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
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!(pxx_req & domain->bits.pxx),
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0, USEC_PER_MSEC);
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if (ret) {
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dev_err(domain->dev, "failed to command PGC\n");
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/*
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* If we were in a process of enabling a
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* domain and failed we might as well disable
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* the regulator we just enabled. And if it
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* was the opposite situation and we failed to
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* power down -- keep the regulator on
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*/
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on = !on;
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}
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if (enable_power_control)
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regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
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GPC_PGC_CTRL_PCR, 0);
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/* Disable reset clocks for all devices in the domain */
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for (i = 0; i < domain->num_clks; i++)
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clk_disable_unprepare(domain->clk[i]);
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if (has_regulator && !on) {
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int err;
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err = regulator_disable(domain->regulator);
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if (err)
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dev_err(domain->dev,
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"failed to disable regulator: %d\n", err);
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/* Preserve earlier error code */
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ret = ret ?: err;
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}
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unmap:
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regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
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domain->bits.map, 0);
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return ret;
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}
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static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
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{
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return imx_gpc_pu_pgc_sw_pxx_req(genpd, true);
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}
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static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
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{
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return imx_gpc_pu_pgc_sw_pxx_req(genpd, false);
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}
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static const struct imx_pgc_domain imx7_pgc_domains[] = {
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[IMX7_POWER_DOMAIN_MIPI_PHY] = {
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.genpd = {
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.name = "mipi-phy",
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},
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.bits = {
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.pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
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.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
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},
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.voltage = 1000000,
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.pgc = IMX7_PGC_MIPI,
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},
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[IMX7_POWER_DOMAIN_PCIE_PHY] = {
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.genpd = {
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.name = "pcie-phy",
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},
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.bits = {
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.pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
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.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
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},
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.voltage = 1000000,
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.pgc = IMX7_PGC_PCIE,
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},
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[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
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.genpd = {
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.name = "usb-hsic-phy",
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},
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.bits = {
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.pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
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.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
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},
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.voltage = 1200000,
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.pgc = IMX7_PGC_USB_HSIC,
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},
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};
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static const struct regmap_range imx7_yes_ranges[] = {
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regmap_reg_range(GPC_LPCR_A_CORE_BSC,
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GPC_M4_PU_PDN_FLG),
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regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
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GPC_PGC_SR(IMX7_PGC_MIPI)),
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regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
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GPC_PGC_SR(IMX7_PGC_PCIE)),
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regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
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GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
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};
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static const struct regmap_access_table imx7_access_table = {
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.yes_ranges = imx7_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
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};
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static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
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.domains = imx7_pgc_domains,
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.domains_num = ARRAY_SIZE(imx7_pgc_domains),
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.reg_access_table = &imx7_access_table,
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};
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static const struct imx_pgc_domain imx8m_pgc_domains[] = {
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[IMX8M_POWER_DOMAIN_MIPI] = {
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.genpd = {
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.name = "mipi",
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},
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.bits = {
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.pxx = IMX8M_MIPI_SW_Pxx_REQ,
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.map = IMX8M_MIPI_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_MIPI,
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},
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[IMX8M_POWER_DOMAIN_PCIE1] = {
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.genpd = {
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.name = "pcie1",
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},
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.bits = {
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.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
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.map = IMX8M_PCIE1_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_PCIE1,
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},
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[IMX8M_POWER_DOMAIN_USB_OTG1] = {
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.genpd = {
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.name = "usb-otg1",
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},
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.bits = {
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.pxx = IMX8M_OTG1_SW_Pxx_REQ,
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.map = IMX8M_OTG1_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_OTG1,
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},
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[IMX8M_POWER_DOMAIN_USB_OTG2] = {
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.genpd = {
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.name = "usb-otg2",
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},
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.bits = {
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.pxx = IMX8M_OTG2_SW_Pxx_REQ,
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.map = IMX8M_OTG2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_OTG2,
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},
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[IMX8M_POWER_DOMAIN_DDR1] = {
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.genpd = {
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.name = "ddr1",
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},
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.bits = {
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.pxx = IMX8M_DDR1_SW_Pxx_REQ,
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.map = IMX8M_DDR2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_DDR1,
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},
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[IMX8M_POWER_DOMAIN_GPU] = {
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.genpd = {
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.name = "gpu",
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},
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.bits = {
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.pxx = IMX8M_GPU_SW_Pxx_REQ,
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.map = IMX8M_GPU_A53_DOMAIN,
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.hsk = IMX8M_GPU_HSK_PWRDNREQN,
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},
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.pgc = IMX8M_PGC_GPU,
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},
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[IMX8M_POWER_DOMAIN_VPU] = {
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.genpd = {
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.name = "vpu",
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},
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.bits = {
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.pxx = IMX8M_VPU_SW_Pxx_REQ,
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.map = IMX8M_VPU_A53_DOMAIN,
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.hsk = IMX8M_VPU_HSK_PWRDNREQN,
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},
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.pgc = IMX8M_PGC_VPU,
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},
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[IMX8M_POWER_DOMAIN_DISP] = {
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.genpd = {
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.name = "disp",
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},
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.bits = {
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.pxx = IMX8M_DISP_SW_Pxx_REQ,
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.map = IMX8M_DISP_A53_DOMAIN,
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.hsk = IMX8M_DISP_HSK_PWRDNREQN,
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},
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.pgc = IMX8M_PGC_DISP,
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},
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[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
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.genpd = {
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.name = "mipi-csi1",
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},
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.bits = {
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.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
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.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_MIPI_CSI1,
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},
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[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
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.genpd = {
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.name = "mipi-csi2",
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},
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.bits = {
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.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
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.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_MIPI_CSI2,
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},
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[IMX8M_POWER_DOMAIN_PCIE2] = {
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.genpd = {
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.name = "pcie2",
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},
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.bits = {
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.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
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.map = IMX8M_PCIE2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_PCIE2,
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},
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};
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static const struct regmap_range imx8m_yes_ranges[] = {
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regmap_reg_range(GPC_LPCR_A_CORE_BSC,
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GPC_PU_PWRHSK),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
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GPC_PGC_SR(IMX8M_PGC_MIPI)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
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GPC_PGC_SR(IMX8M_PGC_PCIE1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
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GPC_PGC_SR(IMX8M_PGC_OTG1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
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GPC_PGC_SR(IMX8M_PGC_OTG2)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
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GPC_PGC_SR(IMX8M_PGC_DDR1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
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GPC_PGC_SR(IMX8M_PGC_GPU)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
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GPC_PGC_SR(IMX8M_PGC_VPU)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
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GPC_PGC_SR(IMX8M_PGC_DISP)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
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GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
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GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
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GPC_PGC_SR(IMX8M_PGC_PCIE2)),
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};
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static const struct regmap_access_table imx8m_access_table = {
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.yes_ranges = imx8m_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges),
|
|
};
|
|
|
|
static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
|
|
.domains = imx8m_pgc_domains,
|
|
.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
|
|
.reg_access_table = &imx8m_access_table,
|
|
};
|
|
|
|
static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
|
|
{
|
|
int i, ret;
|
|
|
|
for (i = 0; ; i++) {
|
|
struct clk *clk = of_clk_get(domain->dev->of_node, i);
|
|
if (IS_ERR(clk))
|
|
break;
|
|
if (i >= GPC_CLK_MAX) {
|
|
dev_err(domain->dev, "more than %d clocks\n",
|
|
GPC_CLK_MAX);
|
|
ret = -EINVAL;
|
|
goto clk_err;
|
|
}
|
|
domain->clk[i] = clk;
|
|
}
|
|
domain->num_clks = i;
|
|
|
|
return 0;
|
|
|
|
clk_err:
|
|
while (i--)
|
|
clk_put(domain->clk[i]);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void imx_pgc_put_clocks(struct imx_pgc_domain *domain)
|
|
{
|
|
int i;
|
|
|
|
for (i = domain->num_clks - 1; i >= 0; i--)
|
|
clk_put(domain->clk[i]);
|
|
}
|
|
|
|
static int imx_pgc_domain_probe(struct platform_device *pdev)
|
|
{
|
|
struct imx_pgc_domain *domain = pdev->dev.platform_data;
|
|
int ret;
|
|
|
|
domain->dev = &pdev->dev;
|
|
|
|
domain->regulator = devm_regulator_get_optional(domain->dev, "power");
|
|
if (IS_ERR(domain->regulator)) {
|
|
if (PTR_ERR(domain->regulator) != -ENODEV) {
|
|
if (PTR_ERR(domain->regulator) != -EPROBE_DEFER)
|
|
dev_err(domain->dev, "Failed to get domain's regulator\n");
|
|
return PTR_ERR(domain->regulator);
|
|
}
|
|
} else if (domain->voltage) {
|
|
regulator_set_voltage(domain->regulator,
|
|
domain->voltage, domain->voltage);
|
|
}
|
|
|
|
ret = imx_pgc_get_clocks(domain);
|
|
if (ret) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(domain->dev, "Failed to get domain's clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = pm_genpd_init(&domain->genpd, NULL, true);
|
|
if (ret) {
|
|
dev_err(domain->dev, "Failed to init power domain\n");
|
|
imx_pgc_put_clocks(domain);
|
|
return ret;
|
|
}
|
|
|
|
ret = of_genpd_add_provider_simple(domain->dev->of_node,
|
|
&domain->genpd);
|
|
if (ret) {
|
|
dev_err(domain->dev, "Failed to add genpd provider\n");
|
|
pm_genpd_remove(&domain->genpd);
|
|
imx_pgc_put_clocks(domain);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int imx_pgc_domain_remove(struct platform_device *pdev)
|
|
{
|
|
struct imx_pgc_domain *domain = pdev->dev.platform_data;
|
|
|
|
of_genpd_del_provider(domain->dev->of_node);
|
|
pm_genpd_remove(&domain->genpd);
|
|
imx_pgc_put_clocks(domain);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id imx_pgc_domain_id[] = {
|
|
{ "imx-pgc-domain", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver imx_pgc_domain_driver = {
|
|
.driver = {
|
|
.name = "imx-pgc",
|
|
},
|
|
.probe = imx_pgc_domain_probe,
|
|
.remove = imx_pgc_domain_remove,
|
|
.id_table = imx_pgc_domain_id,
|
|
};
|
|
builtin_platform_driver(imx_pgc_domain_driver)
|
|
|
|
static int imx_gpcv2_probe(struct platform_device *pdev)
|
|
{
|
|
const struct imx_pgc_domain_data *domain_data =
|
|
of_device_get_match_data(&pdev->dev);
|
|
|
|
struct regmap_config regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.rd_table = domain_data->reg_access_table,
|
|
.wr_table = domain_data->reg_access_table,
|
|
.max_register = SZ_4K,
|
|
};
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *pgc_np, *np;
|
|
struct regmap *regmap;
|
|
void __iomem *base;
|
|
int ret;
|
|
|
|
pgc_np = of_get_child_by_name(dev->of_node, "pgc");
|
|
if (!pgc_np) {
|
|
dev_err(dev, "No power domains specified in DT\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
regmap = devm_regmap_init_mmio(dev, base, ®map_config);
|
|
if (IS_ERR(regmap)) {
|
|
ret = PTR_ERR(regmap);
|
|
dev_err(dev, "failed to init regmap (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
for_each_child_of_node(pgc_np, np) {
|
|
struct platform_device *pd_pdev;
|
|
struct imx_pgc_domain *domain;
|
|
u32 domain_index;
|
|
|
|
ret = of_property_read_u32(np, "reg", &domain_index);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to read 'reg' property\n");
|
|
of_node_put(np);
|
|
return ret;
|
|
}
|
|
|
|
if (domain_index >= domain_data->domains_num) {
|
|
dev_warn(dev,
|
|
"Domain index %d is out of bounds\n",
|
|
domain_index);
|
|
continue;
|
|
}
|
|
|
|
pd_pdev = platform_device_alloc("imx-pgc-domain",
|
|
domain_index);
|
|
if (!pd_pdev) {
|
|
dev_err(dev, "Failed to allocate platform device\n");
|
|
of_node_put(np);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = platform_device_add_data(pd_pdev,
|
|
&domain_data->domains[domain_index],
|
|
sizeof(domain_data->domains[domain_index]));
|
|
if (ret) {
|
|
platform_device_put(pd_pdev);
|
|
of_node_put(np);
|
|
return ret;
|
|
}
|
|
|
|
domain = pd_pdev->dev.platform_data;
|
|
domain->regmap = regmap;
|
|
domain->genpd.power_on = imx_gpc_pu_pgc_sw_pup_req;
|
|
domain->genpd.power_off = imx_gpc_pu_pgc_sw_pdn_req;
|
|
|
|
pd_pdev->dev.parent = dev;
|
|
pd_pdev->dev.of_node = np;
|
|
|
|
ret = platform_device_add(pd_pdev);
|
|
if (ret) {
|
|
platform_device_put(pd_pdev);
|
|
of_node_put(np);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id imx_gpcv2_dt_ids[] = {
|
|
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
|
|
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver imx_gpc_driver = {
|
|
.driver = {
|
|
.name = "imx-gpcv2",
|
|
.of_match_table = imx_gpcv2_dt_ids,
|
|
},
|
|
.probe = imx_gpcv2_probe,
|
|
};
|
|
builtin_platform_driver(imx_gpc_driver)
|