726 lines
16 KiB
C
726 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include "mtk-eint.h"
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#include "pinctrl-mtk-common-v2.h"
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/**
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* struct mtk_drive_desc - the structure that holds the information
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* of the driving current
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* @min: the minimum current of this group
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* @max: the maximum current of this group
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* @step: the step current of this group
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* @scal: the weight factor
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*
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* formula: output = ((input) / step - 1) * scal
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*/
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struct mtk_drive_desc {
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u8 min;
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u8 max;
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u8 step;
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u8 scal;
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};
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/* The groups of drive strength */
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static const struct mtk_drive_desc mtk_drive[] = {
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[DRV_GRP0] = { 4, 16, 4, 1 },
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[DRV_GRP1] = { 4, 16, 4, 2 },
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[DRV_GRP2] = { 2, 8, 2, 1 },
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[DRV_GRP3] = { 2, 8, 2, 2 },
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[DRV_GRP4] = { 2, 16, 2, 1 },
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};
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static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
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{
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writel_relaxed(val, pctl->base[i] + reg);
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}
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static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
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{
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return readl_relaxed(pctl->base[i] + reg);
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}
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void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
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{
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u32 val;
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val = mtk_r32(pctl, i, reg);
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val &= ~mask;
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val |= set;
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mtk_w32(pctl, i, reg, val);
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}
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static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc,
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int field, struct mtk_pin_field *pfd)
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{
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const struct mtk_pin_field_calc *c, *e;
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const struct mtk_pin_reg_calc *rc;
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u32 bits;
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if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
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rc = &hw->soc->reg_cal[field];
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} else {
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dev_dbg(hw->dev,
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"Not support field %d for pin %d (%s)\n",
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field, desc->number, desc->name);
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return -ENOTSUPP;
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}
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c = rc->range;
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e = c + rc->nranges;
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while (c < e) {
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if (desc->number >= c->s_pin && desc->number <= c->e_pin)
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break;
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c++;
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}
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if (c >= e) {
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dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
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field, desc->number, desc->name);
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return -ENOTSUPP;
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}
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if (c->i_base > hw->nbase - 1) {
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dev_err(hw->dev,
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"Invalid base for field %d for pin = %d (%s)\n",
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field, desc->number, desc->name);
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return -EINVAL;
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}
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/* Calculated bits as the overall offset the pin is located at,
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* if c->fixed is held, that determines the all the pins in the
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* range use the same field with the s_pin.
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*/
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bits = c->fixed ? c->s_bit : c->s_bit +
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(desc->number - c->s_pin) * (c->x_bits);
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/* Fill pfd from bits. For example 32-bit register applied is assumed
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* when c->sz_reg is equal to 32.
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*/
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pfd->index = c->i_base;
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pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
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pfd->bitpos = bits % c->sz_reg;
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pfd->mask = (1 << c->x_bits) - 1;
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/* pfd->next is used for indicating that bit wrapping-around happens
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* which requires the manipulation for bit 0 starting in the next
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* register to form the complete field read/write.
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*/
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pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
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return 0;
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}
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static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc,
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int field, struct mtk_pin_field *pfd)
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{
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if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
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dev_err(hw->dev, "Invalid Field %d\n", field);
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return -EINVAL;
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}
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return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
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}
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static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
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{
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*l = 32 - pf->bitpos;
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*h = get_count_order(pf->mask) - *l;
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}
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static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
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struct mtk_pin_field *pf, int value)
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{
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int nbits_l, nbits_h;
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mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
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mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
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(value & pf->mask) << pf->bitpos);
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mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
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(value & pf->mask) >> nbits_l);
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}
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static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
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struct mtk_pin_field *pf, int *value)
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{
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int nbits_l, nbits_h, h, l;
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mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
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l = (mtk_r32(hw, pf->index, pf->offset)
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>> pf->bitpos) & (BIT(nbits_l) - 1);
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h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
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& (BIT(nbits_h) - 1);
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*value = (h << nbits_l) | l;
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}
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int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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int field, int value)
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{
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struct mtk_pin_field pf;
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int err;
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err = mtk_hw_pin_field_get(hw, desc, field, &pf);
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if (err)
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return err;
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if (!pf.next)
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mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
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(value & pf.mask) << pf.bitpos);
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else
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mtk_hw_write_cross_field(hw, &pf, value);
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return 0;
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}
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int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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int field, int *value)
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{
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struct mtk_pin_field pf;
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int err;
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err = mtk_hw_pin_field_get(hw, desc, field, &pf);
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if (err)
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return err;
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if (!pf.next)
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*value = (mtk_r32(hw, pf.index, pf.offset)
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>> pf.bitpos) & pf.mask;
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else
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mtk_hw_read_cross_field(hw, &pf, value);
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return 0;
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}
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static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
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{
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const struct mtk_pin_desc *desc;
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int i = 0;
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desc = (const struct mtk_pin_desc *)hw->soc->pins;
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while (i < hw->soc->npins) {
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if (desc[i].eint.eint_n == eint_n)
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return desc[i].number;
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i++;
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}
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return EINT_NA;
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}
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static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
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unsigned int *gpio_n,
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struct gpio_chip **gpio_chip)
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{
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struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
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const struct mtk_pin_desc *desc;
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desc = (const struct mtk_pin_desc *)hw->soc->pins;
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*gpio_chip = &hw->chip;
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/* Be greedy to guess first gpio_n is equal to eint_n */
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if (desc[eint_n].eint.eint_n == eint_n)
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*gpio_n = eint_n;
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else
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*gpio_n = mtk_xt_find_eint_num(hw, eint_n);
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return *gpio_n == EINT_NA ? -EINVAL : 0;
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}
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static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
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{
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struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
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const struct mtk_pin_desc *desc;
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struct gpio_chip *gpio_chip;
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unsigned int gpio_n;
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int value, err;
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err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
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if (err)
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return err;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
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if (err)
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return err;
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return !!value;
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}
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static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
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{
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struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
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const struct mtk_pin_desc *desc;
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struct gpio_chip *gpio_chip;
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unsigned int gpio_n;
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int err;
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err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
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if (err)
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return err;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
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desc->eint.eint_m);
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if (err)
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return err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
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if (err)
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return err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
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/* SMT is supposed to be supported by every real GPIO and doesn't
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* support virtual GPIOs, so the extra condition err != -ENOTSUPP
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* is just for adding EINT support to these virtual GPIOs. It should
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* add an extra flag in the pin descriptor when more pins with
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* distinctive characteristic come out.
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*/
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if (err && err != -ENOTSUPP)
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return err;
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return 0;
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}
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static const struct mtk_eint_xt mtk_eint_xt = {
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.get_gpio_n = mtk_xt_get_gpio_n,
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.get_gpio_state = mtk_xt_get_gpio_state,
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.set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
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};
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int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct resource *res;
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if (!IS_ENABLED(CONFIG_EINT_MTK))
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return 0;
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if (!of_property_read_bool(np, "interrupt-controller"))
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return -ENODEV;
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hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
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if (!hw->eint)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
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if (!res) {
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dev_err(&pdev->dev, "Unable to get eint resource\n");
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return -ENODEV;
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}
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hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(hw->eint->base))
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return PTR_ERR(hw->eint->base);
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hw->eint->irq = irq_of_parse_and_map(np, 0);
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if (!hw->eint->irq)
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return -EINVAL;
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if (!hw->soc->eint_hw)
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return -ENODEV;
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hw->eint->dev = &pdev->dev;
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hw->eint->hw = hw->soc->eint_hw;
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hw->eint->pctl = hw;
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hw->eint->gpio_xlate = &mtk_eint_xt;
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return mtk_eint_do_init(hw->eint);
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}
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/* Revision 0 */
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int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc)
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{
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int err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
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MTK_DISABLE);
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if (err)
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return err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
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MTK_DISABLE);
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if (err)
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return err;
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return 0;
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}
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int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *res)
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{
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int v, v2;
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int err;
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
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if (err)
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return err;
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
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if (err)
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return err;
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if (v == MTK_ENABLE || v2 == MTK_ENABLE)
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return -EINVAL;
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*res = 1;
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return 0;
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}
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int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup)
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{
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int err, arg;
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arg = pullup ? 1 : 2;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
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if (err)
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return err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
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!!(arg & 2));
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if (err)
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return err;
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return 0;
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}
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int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup, int *res)
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{
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int reg, err, v;
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reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
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err = mtk_hw_get_value(hw, desc, reg, &v);
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if (err)
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return err;
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if (!v)
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return -EINVAL;
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*res = 1;
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return 0;
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}
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/* Revision 1 */
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int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc)
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{
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int err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
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MTK_DISABLE);
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if (err)
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return err;
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return 0;
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}
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int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *res)
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{
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int v, err;
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
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if (err)
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return err;
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if (v == MTK_ENABLE)
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return -EINVAL;
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*res = 1;
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return 0;
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}
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int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup)
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{
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int err, arg;
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arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
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MTK_ENABLE);
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if (err)
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return err;
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
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if (err)
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return err;
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return 0;
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}
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int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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int *res)
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{
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int err, v;
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
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if (err)
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return err;
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if (v == MTK_DISABLE)
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return -EINVAL;
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
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if (err)
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return err;
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if (pullup ^ (v == MTK_PULLUP))
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return -EINVAL;
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*res = 1;
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return 0;
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}
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/* Revision 0 */
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int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg)
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{
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const struct mtk_drive_desc *tb;
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int err = -ENOTSUPP;
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tb = &mtk_drive[desc->drv_n];
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/* 4mA when (e8, e4) = (0, 0)
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* 8mA when (e8, e4) = (0, 1)
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* 12mA when (e8, e4) = (1, 0)
|
|
* 16mA when (e8, e4) = (1, 1)
|
|
*/
|
|
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
|
|
arg = (arg / tb->step - 1) * tb->scal;
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
|
|
arg & 0x1);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
|
|
(arg & 0x2) >> 1);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, int *val)
|
|
{
|
|
const struct mtk_drive_desc *tb;
|
|
int err, val1, val2;
|
|
|
|
tb = &mtk_drive[desc->drv_n];
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
|
|
if (err)
|
|
return err;
|
|
|
|
/* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
|
|
* 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
|
|
*/
|
|
*val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Revision 1 */
|
|
int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, u32 arg)
|
|
{
|
|
const struct mtk_drive_desc *tb;
|
|
int err = -ENOTSUPP;
|
|
|
|
tb = &mtk_drive[desc->drv_n];
|
|
|
|
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
|
|
arg = (arg / tb->step - 1) * tb->scal;
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
|
|
arg);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, int *val)
|
|
{
|
|
const struct mtk_drive_desc *tb;
|
|
int err, val1;
|
|
|
|
tb = &mtk_drive[desc->drv_n];
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
|
|
if (err)
|
|
return err;
|
|
|
|
*val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, bool pullup,
|
|
u32 arg)
|
|
{
|
|
int err;
|
|
|
|
/* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
|
|
* 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
|
|
* 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
|
|
* 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
|
|
*/
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
|
|
if (err)
|
|
return 0;
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
|
|
!!(arg & 2));
|
|
if (err)
|
|
return 0;
|
|
|
|
arg = pullup ? 0 : 1;
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
|
|
|
|
/* If PUPD register is not supported for that pin, let's fallback to
|
|
* general bias control.
|
|
*/
|
|
if (err == -ENOTSUPP) {
|
|
if (hw->soc->bias_set) {
|
|
err = hw->soc->bias_set(hw, desc, pullup);
|
|
if (err)
|
|
return err;
|
|
} else {
|
|
return -ENOTSUPP;
|
|
}
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, bool pullup,
|
|
u32 *val)
|
|
{
|
|
u32 t, t2;
|
|
int err;
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
|
|
|
|
/* If PUPD register is not supported for that pin, let's fallback to
|
|
* general bias control.
|
|
*/
|
|
if (err == -ENOTSUPP) {
|
|
if (hw->soc->bias_get) {
|
|
err = hw->soc->bias_get(hw, desc, pullup, val);
|
|
if (err)
|
|
return err;
|
|
} else {
|
|
return -ENOTSUPP;
|
|
}
|
|
} else {
|
|
/* t == 0 supposes PULLUP for the customized PULL setup */
|
|
if (err)
|
|
return err;
|
|
|
|
if (pullup ^ !t)
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
|
|
if (err)
|
|
return err;
|
|
|
|
*val = (t | t2 << 1) & 0x7;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, u32 arg)
|
|
{
|
|
int err;
|
|
int en = arg & 1;
|
|
int e0 = !!(arg & 2);
|
|
int e1 = !!(arg & 4);
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
|
|
if (err)
|
|
return err;
|
|
|
|
if (!en)
|
|
return err;
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
|
|
if (err)
|
|
return err;
|
|
|
|
return err;
|
|
}
|
|
|
|
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
|
|
const struct mtk_pin_desc *desc, u32 *val)
|
|
{
|
|
u32 en, e0, e1;
|
|
int err;
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
|
|
if (err)
|
|
return err;
|
|
|
|
*val = (en | e0 << 1 | e1 << 2) & 0x7;
|
|
|
|
return 0;
|
|
}
|