1125 lines
36 KiB
C
1125 lines
36 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*
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* Contact Information:
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* Intel Linux Wireless <linuxwifi@intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __iwl_trans_int_pcie_h__
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#define __iwl_trans_int_pcie_h__
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/skbuff.h>
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#include <linux/wait.h>
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#include <linux/pci.h>
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#include <linux/timer.h>
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#include <linux/cpu.h>
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#include "iwl-fh.h"
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#include "iwl-csr.h"
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#include "iwl-trans.h"
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#include "iwl-debug.h"
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#include "iwl-io.h"
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#include "iwl-op-mode.h"
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#include "iwl-drv.h"
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/* We need 2 entries for the TX command and header, and another one might
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* be needed for potential data in the SKB's head. The remaining ones can
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* be used for frags.
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*/
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#define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3)
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/*
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* RX related structures and functions
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*/
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#define RX_NUM_QUEUES 1
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#define RX_POST_REQ_ALLOC 2
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#define RX_CLAIM_REQ_ALLOC 8
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#define RX_PENDING_WATERMARK 16
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#define FIRST_RX_QUEUE 512
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struct iwl_host_cmd;
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/*This file includes the declaration that are internal to the
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* trans_pcie layer */
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/**
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* struct iwl_rx_mem_buffer
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* @page_dma: bus address of rxb page
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* @page: driver's pointer to the rxb page
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* @invalid: rxb is in driver ownership - not owned by HW
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* @vid: index of this rxb in the global table
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*/
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struct iwl_rx_mem_buffer {
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dma_addr_t page_dma;
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struct page *page;
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u16 vid;
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bool invalid;
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struct list_head list;
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};
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/**
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* struct isr_statistics - interrupt statistics
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*
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*/
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struct isr_statistics {
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u32 hw;
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u32 sw;
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u32 err_code;
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u32 sch;
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u32 alive;
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u32 rfkill;
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u32 ctkill;
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u32 wakeup;
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u32 rx;
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u32 tx;
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u32 unhandled;
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};
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/**
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* struct iwl_rx_transfer_desc - transfer descriptor
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* @addr: ptr to free buffer start address
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* @rbid: unique tag of the buffer
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* @reserved: reserved
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*/
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struct iwl_rx_transfer_desc {
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__le16 rbid;
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__le16 reserved[3];
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__le64 addr;
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} __packed;
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#define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
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/**
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* struct iwl_rx_completion_desc - completion descriptor
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* @reserved1: reserved
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* @rbid: unique tag of the received buffer
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* @flags: flags (0: fragmented, all others: reserved)
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* @reserved2: reserved
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*/
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struct iwl_rx_completion_desc {
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__le32 reserved1;
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__le16 rbid;
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u8 flags;
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u8 reserved2[25];
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} __packed;
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/**
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* struct iwl_rxq - Rx queue
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* @id: queue index
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
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* Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
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* In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd)
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* @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd)
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* @tr_tail: driver's pointer to the transmission ring tail buffer
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* @tr_tail_dma: physical address of the buffer for the transmission ring tail
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* @cr_tail: driver's pointer to the completion ring tail buffer
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* @cr_tail_dma: physical address of the buffer for the completion ring tail
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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* @used_count: Number of RBDs handled to allocator to use for allocation
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* @write_actual:
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* @rx_free: list of RBDs with allocated RB ready for use
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* @rx_used: list of RBDs with no RB attached
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* @need_update: flag to indicate we need to update read/write index
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* @rb_stts: driver's pointer to receive buffer status
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* @rb_stts_dma: bus address of receive buffer status
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* @lock:
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* @queue: actual rx queue. Not used for multi-rx queue.
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rxq {
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int id;
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void *bd;
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dma_addr_t bd_dma;
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union {
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void *used_bd;
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__le32 *bd_32;
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struct iwl_rx_completion_desc *cd;
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};
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dma_addr_t used_bd_dma;
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__le16 *tr_tail;
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dma_addr_t tr_tail_dma;
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__le16 *cr_tail;
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dma_addr_t cr_tail_dma;
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u32 read;
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u32 write;
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u32 free_count;
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u32 used_count;
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u32 write_actual;
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u32 queue_size;
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struct list_head rx_free;
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struct list_head rx_used;
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bool need_update;
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void *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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struct napi_struct napi;
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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};
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/**
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* struct iwl_rb_allocator - Rx allocator
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* @req_pending: number of requests the allcator had not processed yet
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* @req_ready: number of requests honored and ready for claiming
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* @rbd_allocated: RBDs with pages allocated and ready to be handled to
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* the queue. This is a list of &struct iwl_rx_mem_buffer
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* @rbd_empty: RBDs with no page attached for allocator use. This is a list
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* of &struct iwl_rx_mem_buffer
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* @lock: protects the rbd_allocated and rbd_empty lists
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* @alloc_wq: work queue for background calls
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* @rx_alloc: work struct for background calls
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*/
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struct iwl_rb_allocator {
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atomic_t req_pending;
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atomic_t req_ready;
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struct list_head rbd_allocated;
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struct list_head rbd_empty;
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spinlock_t lock;
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struct workqueue_struct *alloc_wq;
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struct work_struct rx_alloc;
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};
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struct iwl_dma_ptr {
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dma_addr_t dma;
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void *addr;
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size_t size;
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};
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/**
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* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
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* @index -- current index
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*/
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static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index)
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{
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return ++index &
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(trans->trans_cfg->base_params->max_tfd_queue_size - 1);
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}
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/**
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* iwl_get_closed_rb_stts - get closed rb stts from different structs
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* @rxq - the rxq to get the rb stts from
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*/
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static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
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struct iwl_rxq *rxq)
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{
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
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__le16 *rb_stts = rxq->rb_stts;
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return READ_ONCE(*rb_stts);
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} else {
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struct iwl_rb_status *rb_stts = rxq->rb_stts;
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return READ_ONCE(rb_stts->closed_rb_num);
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}
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}
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/**
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* iwl_queue_dec_wrap - decrement queue index, wrap back to end
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* @index -- current index
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*/
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static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index)
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{
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return --index &
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(trans->trans_cfg->base_params->max_tfd_queue_size - 1);
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}
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struct iwl_cmd_meta {
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/* only for SYNC commands, iff the reply skb is wanted */
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struct iwl_host_cmd *source;
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u32 flags;
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u32 tbs;
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};
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/*
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* The FH will write back to the first TB only, so we need to copy some data
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* into the buffer regardless of whether it should be mapped or not.
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* This indicates how big the first TB must be to include the scratch buffer
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* and the assigned PN.
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* Since PN location is 8 bytes at offset 12, it's 20 now.
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* If we make it bigger then allocations will be bigger and copy slower, so
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* that's probably not useful.
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*/
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#define IWL_FIRST_TB_SIZE 20
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#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
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struct iwl_pcie_txq_entry {
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void *cmd;
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struct sk_buff *skb;
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/* buffer to free after command completes */
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const void *free_buf;
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struct iwl_cmd_meta meta;
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};
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struct iwl_pcie_first_tb_buf {
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u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
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};
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/**
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* struct iwl_txq - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @tfds: transmit frame descriptors (DMA memory)
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* @first_tb_bufs: start of command headers, including scratch buffers, for
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* the writeback -- this is DMA memory and an array holding one buffer
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* for each command on the queue
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* @first_tb_dma: DMA address for the first_tb_bufs start
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* @entries: transmit entries (driver state)
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* @lock: queue lock
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* @stuck_timer: timer that fires if queue gets stuck
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* @trans_pcie: pointer back to transport (for timer)
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* @need_update: indicates need to update read/write index
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* @ampdu: true if this queue is an ampdu queue for an specific RA/TID
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* @wd_timeout: queue watchdog timeout (jiffies) - per queue
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* @frozen: tx stuck queue timer is frozen
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* @frozen_expiry_remainder: remember how long until the timer fires
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* @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
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* @write_ptr: 1-st empty entry (index) host_w
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* @read_ptr: last used entry (index) host_r
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* @dma_addr: physical addr for BD's
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* @n_window: safe queue window
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* @id: queue id
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* @low_mark: low watermark, resume queue if free space more than this
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* @high_mark: high watermark, stop queue if free space less than this
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*
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*
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* Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
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* always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
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* there might be HW changes in the future). For the normal TX
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* queues, n_window, which is the size of the software queue data
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* is also 256; however, for the command queue, n_window is only
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
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* This means that we end up with the following:
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* HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
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* SW entries: | 0 | ... | 31 |
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* where N is a number between 0 and 7. This means that the SW
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* data is a window overlayed over the HW queue.
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*/
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struct iwl_txq {
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void *tfds;
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struct iwl_pcie_first_tb_buf *first_tb_bufs;
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dma_addr_t first_tb_dma;
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struct iwl_pcie_txq_entry *entries;
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spinlock_t lock;
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unsigned long frozen_expiry_remainder;
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struct timer_list stuck_timer;
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struct iwl_trans_pcie *trans_pcie;
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bool need_update;
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bool frozen;
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bool ampdu;
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int block;
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unsigned long wd_timeout;
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struct sk_buff_head overflow_q;
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struct iwl_dma_ptr bc_tbl;
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int write_ptr;
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int read_ptr;
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dma_addr_t dma_addr;
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int n_window;
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u32 id;
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int low_mark;
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int high_mark;
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bool overflow_tx;
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};
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static inline dma_addr_t
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iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx)
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{
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return txq->first_tb_dma +
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sizeof(struct iwl_pcie_first_tb_buf) * idx;
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}
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struct iwl_tso_hdr_page {
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struct page *page;
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u8 *pos;
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};
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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/**
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* enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
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* debugfs file
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*
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* @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
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* @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
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* @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
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* set the file can no longer be used.
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*/
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enum iwl_fw_mon_dbgfs_state {
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IWL_FW_MON_DBGFS_STATE_CLOSED,
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IWL_FW_MON_DBGFS_STATE_OPEN,
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IWL_FW_MON_DBGFS_STATE_DISABLED,
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};
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#endif
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/**
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* enum iwl_shared_irq_flags - level of sharing for irq
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* @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
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* @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
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*/
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enum iwl_shared_irq_flags {
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IWL_SHARED_IRQ_NON_RX = BIT(0),
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IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
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};
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/**
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* enum iwl_image_response_code - image response values
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* @IWL_IMAGE_RESP_DEF: the default value of the register
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* @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
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* @IWL_IMAGE_RESP_FAIL: iml reading failed
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*/
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enum iwl_image_response_code {
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IWL_IMAGE_RESP_DEF = 0,
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IWL_IMAGE_RESP_SUCCESS = 1,
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IWL_IMAGE_RESP_FAIL = 2,
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};
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/**
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* struct cont_rec: continuous recording data structure
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* @prev_wr_ptr: the last address that was read in monitor_data
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* debugfs file
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* @prev_wrap_cnt: the wrap count that was used during the last read in
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* monitor_data debugfs file
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* @state: the state of monitor_data debugfs file as described
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* in &iwl_fw_mon_dbgfs_state enum
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* @mutex: locked while reading from monitor_data debugfs file
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*/
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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struct cont_rec {
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u32 prev_wr_ptr;
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u32 prev_wrap_cnt;
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u8 state;
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/* Used to sync monitor_data debugfs file with driver unload flow */
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struct mutex mutex;
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};
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#endif
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
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* @global_table: table mapping received VID from hw to rxb
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* @rba: allocator for RX replenishing
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* @ctxt_info: context information for FW self init
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* @ctxt_info_gen3: context information for gen3 devices
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* @prph_info: prph info for self init
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* @prph_scratch: prph scratch for self init
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* @ctxt_info_dma_addr: dma addr of context information
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* @prph_info_dma_addr: dma addr of prph info
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* @prph_scratch_dma_addr: dma addr of prph scratch
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* @ctxt_info_dma_addr: dma addr of context information
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* @init_dram: DRAM data of firmware image (including paging).
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* Context information addresses will be taken from here.
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* This is driver's local copy for keeping track of size and
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* count for allocating and freeing the memory.
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* @trans: pointer to the generic transport area
|
|
* @scd_base_addr: scheduler sram base address in SRAM
|
|
* @scd_bc_tbls: pointer to the byte count table of the scheduler
|
|
* @kw: keep warm address
|
|
* @pci_dev: basic pci-network driver stuff
|
|
* @hw_base: pci hardware address support
|
|
* @ucode_write_complete: indicates that the ucode has been copied.
|
|
* @ucode_write_waitq: wait queue for uCode load
|
|
* @cmd_queue - command queue number
|
|
* @def_rx_queue - default rx queue number
|
|
* @rx_buf_size: Rx buffer size
|
|
* @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
|
|
* @scd_set_active: should the transport configure the SCD for HCMD queue
|
|
* @sw_csum_tx: if true, then the transport will compute the csum of the TXed
|
|
* frame.
|
|
* @rx_page_order: page order for receive buffer size
|
|
* @reg_lock: protect hw register access
|
|
* @mutex: to protect stop_device / start_fw / start_hw
|
|
* @cmd_in_flight: true when we have a host command in flight
|
|
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
|
* @fw_mon_data: fw continuous recording data
|
|
#endif
|
|
* @msix_entries: array of MSI-X entries
|
|
* @msix_enabled: true if managed to enable MSI-X
|
|
* @shared_vec_mask: the type of causes the shared vector handles
|
|
* (see iwl_shared_irq_flags).
|
|
* @alloc_vecs: the number of interrupt vectors allocated by the OS
|
|
* @def_irq: default irq for non rx causes
|
|
* @fh_init_mask: initial unmasked fh causes
|
|
* @hw_init_mask: initial unmasked hw causes
|
|
* @fh_mask: current unmasked fh causes
|
|
* @hw_mask: current unmasked hw causes
|
|
* @in_rescan: true if we have triggered a device rescan
|
|
* @base_rb_stts: base virtual address of receive buffer status for all queues
|
|
* @base_rb_stts_dma: base physical address of receive buffer status
|
|
*/
|
|
struct iwl_trans_pcie {
|
|
struct iwl_rxq *rxq;
|
|
struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE];
|
|
struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE];
|
|
struct iwl_rb_allocator rba;
|
|
union {
|
|
struct iwl_context_info *ctxt_info;
|
|
struct iwl_context_info_gen3 *ctxt_info_gen3;
|
|
};
|
|
struct iwl_prph_info *prph_info;
|
|
struct iwl_prph_scratch *prph_scratch;
|
|
dma_addr_t ctxt_info_dma_addr;
|
|
dma_addr_t prph_info_dma_addr;
|
|
dma_addr_t prph_scratch_dma_addr;
|
|
dma_addr_t iml_dma_addr;
|
|
struct iwl_trans *trans;
|
|
|
|
struct net_device napi_dev;
|
|
|
|
struct __percpu iwl_tso_hdr_page *tso_hdr_page;
|
|
|
|
/* INT ICT Table */
|
|
__le32 *ict_tbl;
|
|
dma_addr_t ict_tbl_dma;
|
|
int ict_index;
|
|
bool use_ict;
|
|
bool is_down, opmode_down;
|
|
s8 debug_rfkill;
|
|
struct isr_statistics isr_stats;
|
|
|
|
spinlock_t irq_lock;
|
|
struct mutex mutex;
|
|
u32 inta_mask;
|
|
u32 scd_base_addr;
|
|
struct iwl_dma_ptr scd_bc_tbls;
|
|
struct iwl_dma_ptr kw;
|
|
|
|
struct iwl_txq *txq_memory;
|
|
struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
|
|
unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
|
|
unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
|
|
|
|
/* PCI bus related data */
|
|
struct pci_dev *pci_dev;
|
|
void __iomem *hw_base;
|
|
|
|
bool ucode_write_complete;
|
|
bool sx_complete;
|
|
wait_queue_head_t ucode_write_waitq;
|
|
wait_queue_head_t wait_command_queue;
|
|
wait_queue_head_t sx_waitq;
|
|
|
|
u8 page_offs, dev_cmd_offs;
|
|
|
|
u8 cmd_queue;
|
|
u8 def_rx_queue;
|
|
u8 cmd_fifo;
|
|
unsigned int cmd_q_wdg_timeout;
|
|
u8 n_no_reclaim_cmds;
|
|
u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
|
|
u8 max_tbs;
|
|
u16 tfd_size;
|
|
|
|
enum iwl_amsdu_size rx_buf_size;
|
|
bool bc_table_dword;
|
|
bool scd_set_active;
|
|
bool sw_csum_tx;
|
|
bool pcie_dbg_dumped_once;
|
|
u32 rx_page_order;
|
|
|
|
/*protect hw register */
|
|
spinlock_t reg_lock;
|
|
bool cmd_hold_nic_awake;
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
|
struct cont_rec fw_mon_data;
|
|
#endif
|
|
|
|
struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
|
|
bool msix_enabled;
|
|
u8 shared_vec_mask;
|
|
u32 alloc_vecs;
|
|
u32 def_irq;
|
|
u32 fh_init_mask;
|
|
u32 hw_init_mask;
|
|
u32 fh_mask;
|
|
u32 hw_mask;
|
|
cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
|
|
u16 tx_cmd_queue_size;
|
|
bool in_rescan;
|
|
|
|
void *base_rb_stts;
|
|
dma_addr_t base_rb_stts_dma;
|
|
};
|
|
|
|
static inline struct iwl_trans_pcie *
|
|
IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
|
|
{
|
|
return (void *)trans->trans_specific;
|
|
}
|
|
|
|
static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
|
|
struct msix_entry *entry)
|
|
{
|
|
/*
|
|
* Before sending the interrupt the HW disables it to prevent
|
|
* a nested interrupt. This is done by writing 1 to the corresponding
|
|
* bit in the mask register. After handling the interrupt, it should be
|
|
* re-enabled by clearing this bit. This register is defined as
|
|
* write 1 clear (W1C) register, meaning that it's being clear
|
|
* by writing 1 to the bit.
|
|
*/
|
|
iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
|
|
}
|
|
|
|
static inline struct iwl_trans *
|
|
iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
|
|
{
|
|
return container_of((void *)trans_pcie, struct iwl_trans,
|
|
trans_specific);
|
|
}
|
|
|
|
/*
|
|
* Convention: trans API functions: iwl_trans_pcie_XXX
|
|
* Other functions: iwl_pcie_XXX
|
|
*/
|
|
struct iwl_trans
|
|
*iwl_trans_pcie_alloc(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent,
|
|
const struct iwl_cfg_trans_params *cfg_trans);
|
|
void iwl_trans_pcie_free(struct iwl_trans *trans);
|
|
|
|
/*****************************************************
|
|
* RX
|
|
******************************************************/
|
|
int _iwl_pcie_rx_init(struct iwl_trans *trans);
|
|
int iwl_pcie_rx_init(struct iwl_trans *trans);
|
|
int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
|
|
irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
|
|
irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
|
|
irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
|
|
irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
|
|
int iwl_pcie_rx_stop(struct iwl_trans *trans);
|
|
void iwl_pcie_rx_free(struct iwl_trans *trans);
|
|
void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
|
|
void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
|
|
int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget);
|
|
void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
|
|
struct iwl_rxq *rxq);
|
|
int iwl_pcie_rx_alloc(struct iwl_trans *trans);
|
|
|
|
/*****************************************************
|
|
* ICT - interrupt handling
|
|
******************************************************/
|
|
irqreturn_t iwl_pcie_isr(int irq, void *data);
|
|
int iwl_pcie_alloc_ict(struct iwl_trans *trans);
|
|
void iwl_pcie_free_ict(struct iwl_trans *trans);
|
|
void iwl_pcie_reset_ict(struct iwl_trans *trans);
|
|
void iwl_pcie_disable_ict(struct iwl_trans *trans);
|
|
|
|
/*****************************************************
|
|
* TX / HCMD
|
|
******************************************************/
|
|
int iwl_pcie_tx_init(struct iwl_trans *trans);
|
|
int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id,
|
|
int queue_size);
|
|
void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
|
|
int iwl_pcie_tx_stop(struct iwl_trans *trans);
|
|
void iwl_pcie_tx_free(struct iwl_trans *trans);
|
|
bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
|
|
const struct iwl_trans_txq_scd_cfg *cfg,
|
|
unsigned int wdg_timeout);
|
|
void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
|
|
bool configure_scd);
|
|
void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
|
|
bool shared_mode);
|
|
void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans,
|
|
struct iwl_txq *txq);
|
|
int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
|
struct iwl_device_tx_cmd *dev_cmd, int txq_id);
|
|
void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
|
|
int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
|
|
void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx);
|
|
void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
|
|
struct iwl_txq *txq);
|
|
void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
|
|
struct iwl_rx_cmd_buffer *rxb);
|
|
void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
|
|
struct sk_buff_head *skbs);
|
|
void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
|
|
void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
|
|
void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie,
|
|
struct iwl_txq *txq, u16 byte_cnt,
|
|
int num_tbs);
|
|
|
|
static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
|
|
u8 idx)
|
|
{
|
|
if (trans->trans_cfg->use_tfh) {
|
|
struct iwl_tfh_tfd *tfd = _tfd;
|
|
struct iwl_tfh_tb *tb = &tfd->tbs[idx];
|
|
|
|
return le16_to_cpu(tb->tb_len);
|
|
} else {
|
|
struct iwl_tfd *tfd = _tfd;
|
|
struct iwl_tfd_tb *tb = &tfd->tbs[idx];
|
|
|
|
return le16_to_cpu(tb->hi_n_len) >> 4;
|
|
}
|
|
}
|
|
|
|
/*****************************************************
|
|
* Error handling
|
|
******************************************************/
|
|
void iwl_pcie_dump_csr(struct iwl_trans *trans);
|
|
|
|
/*****************************************************
|
|
* Helpers
|
|
******************************************************/
|
|
static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
clear_bit(STATUS_INT_ENABLED, &trans->status);
|
|
if (!trans_pcie->msix_enabled) {
|
|
/* disable interrupts from uCode/NIC to host */
|
|
iwl_write32(trans, CSR_INT_MASK, 0x00000000);
|
|
|
|
/* acknowledge/clear/reset any interrupts still pending
|
|
* from uCode or flow handler (Rx/Tx DMA) */
|
|
iwl_write32(trans, CSR_INT, 0xffffffff);
|
|
iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
|
|
} else {
|
|
/* disable all the interrupt we might use */
|
|
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
|
|
trans_pcie->fh_init_mask);
|
|
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
|
|
trans_pcie->hw_init_mask);
|
|
}
|
|
IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
|
|
}
|
|
|
|
#define IWL_NUM_OF_COMPLETION_RINGS 31
|
|
#define IWL_NUM_OF_TRANSFER_RINGS 527
|
|
|
|
static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
|
|
int start)
|
|
{
|
|
int i = 0;
|
|
|
|
while (start < fw->num_sec &&
|
|
fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
|
|
fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
|
|
start++;
|
|
i++;
|
|
}
|
|
|
|
return i;
|
|
}
|
|
|
|
static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
|
|
const struct fw_desc *sec,
|
|
struct iwl_dram_data *dram)
|
|
{
|
|
dram->block = dma_alloc_coherent(trans->dev, sec->len,
|
|
&dram->physical,
|
|
GFP_KERNEL);
|
|
if (!dram->block)
|
|
return -ENOMEM;
|
|
|
|
dram->size = sec->len;
|
|
memcpy(dram->block, sec->data, sec->len);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_self_init_dram *dram = &trans->init_dram;
|
|
int i;
|
|
|
|
if (!dram->fw) {
|
|
WARN_ON(dram->fw_cnt);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < dram->fw_cnt; i++)
|
|
dma_free_coherent(trans->dev, dram->fw[i].size,
|
|
dram->fw[i].block, dram->fw[i].physical);
|
|
|
|
kfree(dram->fw);
|
|
dram->fw_cnt = 0;
|
|
dram->fw = NULL;
|
|
}
|
|
|
|
static inline void iwl_disable_interrupts(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
spin_lock(&trans_pcie->irq_lock);
|
|
_iwl_disable_interrupts(trans);
|
|
spin_unlock(&trans_pcie->irq_lock);
|
|
}
|
|
|
|
static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
|
|
set_bit(STATUS_INT_ENABLED, &trans->status);
|
|
if (!trans_pcie->msix_enabled) {
|
|
trans_pcie->inta_mask = CSR_INI_SET_MASK;
|
|
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
|
|
} else {
|
|
/*
|
|
* fh/hw_mask keeps all the unmasked causes.
|
|
* Unlike msi, in msix cause is enabled when it is unset.
|
|
*/
|
|
trans_pcie->hw_mask = trans_pcie->hw_init_mask;
|
|
trans_pcie->fh_mask = trans_pcie->fh_init_mask;
|
|
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
|
|
~trans_pcie->fh_mask);
|
|
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
|
|
~trans_pcie->hw_mask);
|
|
}
|
|
}
|
|
|
|
static inline void iwl_enable_interrupts(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
spin_lock(&trans_pcie->irq_lock);
|
|
_iwl_enable_interrupts(trans);
|
|
spin_unlock(&trans_pcie->irq_lock);
|
|
}
|
|
static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
|
|
trans_pcie->hw_mask = msk;
|
|
}
|
|
|
|
static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
|
|
trans_pcie->fh_mask = msk;
|
|
}
|
|
|
|
static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
|
|
if (!trans_pcie->msix_enabled) {
|
|
trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
|
|
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
|
|
} else {
|
|
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
|
|
trans_pcie->hw_init_mask);
|
|
iwl_enable_fh_int_msk_msix(trans,
|
|
MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
|
|
}
|
|
}
|
|
|
|
static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
|
|
|
|
if (!trans_pcie->msix_enabled) {
|
|
/*
|
|
* When we'll receive the ALIVE interrupt, the ISR will call
|
|
* iwl_enable_fw_load_int_ctx_info again to set the ALIVE
|
|
* interrupt (which is not really needed anymore) but also the
|
|
* RX interrupt which will allow us to receive the ALIVE
|
|
* notification (which is Rx) and continue the flow.
|
|
*/
|
|
trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
|
|
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
|
|
} else {
|
|
iwl_enable_hw_int_msk_msix(trans,
|
|
MSIX_HW_INT_CAUSES_REG_ALIVE);
|
|
/*
|
|
* Leave all the FH causes enabled to get the ALIVE
|
|
* notification.
|
|
*/
|
|
iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
|
|
}
|
|
}
|
|
|
|
static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index)
|
|
{
|
|
return index & (q->n_window - 1);
|
|
}
|
|
|
|
static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans,
|
|
struct iwl_txq *txq, int idx)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
if (trans->trans_cfg->use_tfh)
|
|
idx = iwl_pcie_get_cmd_index(txq, idx);
|
|
|
|
return txq->tfds + trans_pcie->tfd_size * idx;
|
|
}
|
|
|
|
static inline const char *queue_name(struct device *dev,
|
|
struct iwl_trans_pcie *trans_p, int i)
|
|
{
|
|
if (trans_p->shared_vec_mask) {
|
|
int vec = trans_p->shared_vec_mask &
|
|
IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
|
|
|
|
if (i == 0)
|
|
return DRV_NAME ": shared IRQ";
|
|
|
|
return devm_kasprintf(dev, GFP_KERNEL,
|
|
DRV_NAME ": queue %d", i + vec);
|
|
}
|
|
if (i == 0)
|
|
return DRV_NAME ": default queue";
|
|
|
|
if (i == trans_p->alloc_vecs - 1)
|
|
return DRV_NAME ": exception";
|
|
|
|
return devm_kasprintf(dev, GFP_KERNEL,
|
|
DRV_NAME ": queue %d", i);
|
|
}
|
|
|
|
static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
|
|
if (!trans_pcie->msix_enabled) {
|
|
trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
|
|
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
|
|
} else {
|
|
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
|
|
trans_pcie->fh_init_mask);
|
|
iwl_enable_hw_int_msk_msix(trans,
|
|
MSIX_HW_INT_CAUSES_REG_RF_KILL);
|
|
}
|
|
|
|
if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
|
|
/*
|
|
* On 9000-series devices this bit isn't enabled by default, so
|
|
* when we power down the device we need set the bit to allow it
|
|
* to wake up the PCI-E bus for RF-kill interrupts.
|
|
*/
|
|
iwl_set_bit(trans, CSR_GP_CNTRL,
|
|
CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
|
|
}
|
|
}
|
|
|
|
void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
|
|
|
|
static inline void iwl_wake_queue(struct iwl_trans *trans,
|
|
struct iwl_txq *txq)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) {
|
|
IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
|
|
iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
|
|
}
|
|
}
|
|
|
|
static inline void iwl_stop_queue(struct iwl_trans *trans,
|
|
struct iwl_txq *txq)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) {
|
|
iwl_op_mode_queue_full(trans->op_mode, txq->id);
|
|
IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
|
|
} else
|
|
IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
|
|
txq->id);
|
|
}
|
|
|
|
static inline bool iwl_queue_used(const struct iwl_txq *q, int i)
|
|
{
|
|
int index = iwl_pcie_get_cmd_index(q, i);
|
|
int r = iwl_pcie_get_cmd_index(q, q->read_ptr);
|
|
int w = iwl_pcie_get_cmd_index(q, q->write_ptr);
|
|
|
|
return w >= r ?
|
|
(index >= r && index < w) :
|
|
!(index < r && index >= w);
|
|
}
|
|
|
|
static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
lockdep_assert_held(&trans_pcie->mutex);
|
|
|
|
if (trans_pcie->debug_rfkill == 1)
|
|
return true;
|
|
|
|
return !(iwl_read32(trans, CSR_GP_CNTRL) &
|
|
CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
|
|
}
|
|
|
|
static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
|
|
u32 reg, u32 mask, u32 value)
|
|
{
|
|
u32 v;
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
WARN_ON_ONCE(value & ~mask);
|
|
#endif
|
|
|
|
v = iwl_read32(trans, reg);
|
|
v &= ~mask;
|
|
v |= value;
|
|
iwl_write32(trans, reg, v);
|
|
}
|
|
|
|
static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
|
|
u32 reg, u32 mask)
|
|
{
|
|
__iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
|
|
}
|
|
|
|
static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
|
|
u32 reg, u32 mask)
|
|
{
|
|
__iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
|
|
}
|
|
|
|
static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
|
|
{
|
|
return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
|
|
}
|
|
|
|
void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
|
|
void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
|
|
void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans);
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
|
void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
|
|
#else
|
|
static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
|
|
#endif
|
|
|
|
void iwl_pcie_rx_allocator_work(struct work_struct *data);
|
|
|
|
/* common functions that are used by gen2 transport */
|
|
int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
|
|
void iwl_pcie_apm_config(struct iwl_trans *trans);
|
|
int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
|
|
void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
|
|
bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
|
|
void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
|
|
bool was_in_rfkill);
|
|
void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
|
|
int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q);
|
|
void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
|
|
void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
|
|
int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
|
|
int slots_num, bool cmd_queue);
|
|
int iwl_pcie_txq_alloc(struct iwl_trans *trans,
|
|
struct iwl_txq *txq, int slots_num, bool cmd_queue);
|
|
int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
|
|
struct iwl_dma_ptr *ptr, size_t size);
|
|
void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
|
|
void iwl_pcie_apply_destination(struct iwl_trans *trans);
|
|
void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
|
|
struct sk_buff *skb);
|
|
#ifdef CONFIG_INET
|
|
struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len);
|
|
#endif
|
|
|
|
/* common functions that are used by gen3 transport */
|
|
void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
|
|
|
|
/* transport gen 2 exported functions */
|
|
int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
|
|
const struct fw_img *fw, bool run_in_rfkill);
|
|
void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
|
|
void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
|
|
struct iwl_txq *txq);
|
|
int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans,
|
|
struct iwl_txq **intxq, int size,
|
|
unsigned int timeout);
|
|
int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans,
|
|
struct iwl_txq *txq,
|
|
struct iwl_host_cmd *hcmd);
|
|
int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
|
|
__le16 flags, u8 sta_id, u8 tid,
|
|
int cmd_id, int size,
|
|
unsigned int timeout);
|
|
void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue);
|
|
int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
|
struct iwl_device_tx_cmd *dev_cmd, int txq_id);
|
|
int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
|
|
struct iwl_host_cmd *cmd);
|
|
void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
|
|
void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
|
|
void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id);
|
|
void iwl_pcie_gen2_tx_free(struct iwl_trans *trans);
|
|
void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans);
|
|
void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
|
|
bool test, bool reset);
|
|
#endif /* __iwl_trans_int_pcie_h__ */
|