717 lines
19 KiB
C
717 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Hitachi SCA HD64570 driver for Linux
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*
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* Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* Source of information: Hitachi HD64570 SCA User's Manual
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*
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* We use the following SCA memory map:
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*
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* Packet buffer descriptor rings - starting from winbase or win0base:
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* rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
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* tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
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* rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
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* tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
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*
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* Packet data buffers - starting from winbase + buff_offset:
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* rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
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* tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
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* rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
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* tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/fcntl.h>
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#include <linux/hdlc.h>
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#include <linux/in.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/skbuff.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <linux/uaccess.h>
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#include "hd64570.h"
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#define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
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#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
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#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
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#define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
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#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
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#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
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static inline struct net_device *port_to_dev(port_t *port)
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{
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return port->dev;
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}
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static inline int sca_intr_status(card_t *card)
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{
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u8 result = 0;
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u8 isr0 = sca_in(ISR0, card);
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u8 isr1 = sca_in(ISR1, card);
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if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
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if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
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if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
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if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
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if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
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if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
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if (!(result & SCA_INTR_DMAC_TX(0)))
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if (sca_in(DSR_TX(0), card) & DSR_EOM)
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result |= SCA_INTR_DMAC_TX(0);
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if (!(result & SCA_INTR_DMAC_TX(1)))
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if (sca_in(DSR_TX(1), card) & DSR_EOM)
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result |= SCA_INTR_DMAC_TX(1);
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return result;
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}
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static inline port_t* dev_to_port(struct net_device *dev)
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{
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return dev_to_hdlc(dev)->priv;
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}
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static inline u16 next_desc(port_t *port, u16 desc, int transmit)
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{
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return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
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: port_to_card(port)->rx_ring_buffers);
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}
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static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
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{
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u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
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u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
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desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
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return log_node(port) * (rx_buffs + tx_buffs) +
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transmit * rx_buffs + desc;
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}
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static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
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{
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/* Descriptor offset always fits in 16 bits */
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return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
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}
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static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
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int transmit)
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{
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#ifdef PAGE0_ALWAYS_MAPPED
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return (pkt_desc __iomem *)(win0base(port_to_card(port))
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+ desc_offset(port, desc, transmit));
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#else
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return (pkt_desc __iomem *)(winbase(port_to_card(port))
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+ desc_offset(port, desc, transmit));
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#endif
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}
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static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
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{
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return port_to_card(port)->buff_offset +
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desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
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}
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static inline void sca_set_carrier(port_t *port)
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{
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if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
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#ifdef DEBUG_LINK
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printk(KERN_DEBUG "%s: sca_set_carrier on\n",
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port_to_dev(port)->name);
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#endif
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netif_carrier_on(port_to_dev(port));
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} else {
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#ifdef DEBUG_LINK
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printk(KERN_DEBUG "%s: sca_set_carrier off\n",
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port_to_dev(port)->name);
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#endif
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netif_carrier_off(port_to_dev(port));
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}
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}
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static void sca_init_port(port_t *port)
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{
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card_t *card = port_to_card(port);
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int transmit, i;
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port->rxin = 0;
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port->txin = 0;
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port->txlast = 0;
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#ifndef PAGE0_ALWAYS_MAPPED
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openwin(card, 0);
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#endif
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for (transmit = 0; transmit < 2; transmit++) {
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u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
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u16 buffs = transmit ? card->tx_ring_buffers
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: card->rx_ring_buffers;
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for (i = 0; i < buffs; i++) {
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pkt_desc __iomem *desc = desc_address(port, i, transmit);
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u16 chain_off = desc_offset(port, i + 1, transmit);
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u32 buff_off = buffer_offset(port, i, transmit);
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writew(chain_off, &desc->cp);
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writel(buff_off, &desc->bp);
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writew(0, &desc->len);
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writeb(0, &desc->stat);
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}
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/* DMA disable - to halt state */
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sca_out(0, transmit ? DSR_TX(phy_node(port)) :
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DSR_RX(phy_node(port)), card);
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/* software ABORT - to initial state */
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sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
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DCR_RX(phy_node(port)), card);
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/* current desc addr */
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sca_out(0, dmac + CPB, card); /* pointer base */
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sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
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if (!transmit)
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sca_outw(desc_offset(port, buffs - 1, transmit),
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dmac + EDAL, card);
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else
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sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
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card);
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/* clear frame end interrupt counter */
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sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
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DCR_RX(phy_node(port)), card);
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if (!transmit) { /* Receive */
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/* set buffer length */
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sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
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/* Chain mode, Multi-frame */
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sca_out(0x14, DMR_RX(phy_node(port)), card);
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sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
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card);
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/* DMA enable */
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sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
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} else { /* Transmit */
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/* Chain mode, Multi-frame */
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sca_out(0x14, DMR_TX(phy_node(port)), card);
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/* enable underflow interrupts */
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sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
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}
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}
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sca_set_carrier(port);
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}
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#ifdef NEED_SCA_MSCI_INTR
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/* MSCI interrupt service */
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static inline void sca_msci_intr(port_t *port)
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{
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u16 msci = get_msci(port);
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card_t* card = port_to_card(port);
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u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
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/* Reset MSCI TX underrun and CDCD status bit */
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sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
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if (stat & ST1_UDRN) {
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/* TX Underrun error detected */
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port_to_dev(port)->stats.tx_errors++;
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port_to_dev(port)->stats.tx_fifo_errors++;
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}
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if (stat & ST1_CDCD)
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sca_set_carrier(port);
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}
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#endif
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static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
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u16 rxin)
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{
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struct net_device *dev = port_to_dev(port);
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struct sk_buff *skb;
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u16 len;
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u32 buff;
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u32 maxlen;
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u8 page;
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len = readw(&desc->len);
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skb = dev_alloc_skb(len);
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if (!skb) {
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dev->stats.rx_dropped++;
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return;
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}
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buff = buffer_offset(port, rxin, 0);
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page = buff / winsize(card);
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buff = buff % winsize(card);
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maxlen = winsize(card) - buff;
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openwin(card, page);
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if (len > maxlen) {
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memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
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openwin(card, page + 1);
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memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
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} else
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memcpy_fromio(skb->data, winbase(card) + buff, len);
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#ifndef PAGE0_ALWAYS_MAPPED
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openwin(card, 0); /* select pkt_desc table page back */
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#endif
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skb_put(skb, len);
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#ifdef DEBUG_PKT
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printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
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debug_frame(skb);
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#endif
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += skb->len;
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skb->protocol = hdlc_type_trans(skb, dev);
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netif_rx(skb);
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}
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/* Receive DMA interrupt service */
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static inline void sca_rx_intr(port_t *port)
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{
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struct net_device *dev = port_to_dev(port);
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u16 dmac = get_dmac_rx(port);
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card_t *card = port_to_card(port);
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u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
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/* Reset DSR status bits */
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sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
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DSR_RX(phy_node(port)), card);
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if (stat & DSR_BOF)
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/* Dropped one or more frames */
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dev->stats.rx_over_errors++;
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while (1) {
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u32 desc_off = desc_offset(port, port->rxin, 0);
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pkt_desc __iomem *desc;
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u32 cda = sca_inw(dmac + CDAL, card);
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if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
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break; /* No frame received */
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desc = desc_address(port, port->rxin, 0);
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stat = readb(&desc->stat);
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if (!(stat & ST_RX_EOM))
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port->rxpart = 1; /* partial frame received */
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else if ((stat & ST_ERROR_MASK) || port->rxpart) {
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dev->stats.rx_errors++;
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if (stat & ST_RX_OVERRUN)
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dev->stats.rx_fifo_errors++;
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else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
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ST_RX_RESBIT)) || port->rxpart)
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dev->stats.rx_frame_errors++;
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else if (stat & ST_RX_CRC)
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dev->stats.rx_crc_errors++;
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if (stat & ST_RX_EOM)
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port->rxpart = 0; /* received last fragment */
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} else
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sca_rx(card, port, desc, port->rxin);
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/* Set new error descriptor address */
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sca_outw(desc_off, dmac + EDAL, card);
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port->rxin = next_desc(port, port->rxin, 0);
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}
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/* make sure RX DMA is enabled */
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sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
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}
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/* Transmit DMA interrupt service */
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static inline void sca_tx_intr(port_t *port)
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{
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struct net_device *dev = port_to_dev(port);
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u16 dmac = get_dmac_tx(port);
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card_t* card = port_to_card(port);
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u8 stat;
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spin_lock(&port->lock);
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stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
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/* Reset DSR status bits */
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sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
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DSR_TX(phy_node(port)), card);
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while (1) {
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pkt_desc __iomem *desc;
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u32 desc_off = desc_offset(port, port->txlast, 1);
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u32 cda = sca_inw(dmac + CDAL, card);
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if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
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break; /* Transmitter is/will_be sending this frame */
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desc = desc_address(port, port->txlast, 1);
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += readw(&desc->len);
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writeb(0, &desc->stat); /* Free descriptor */
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port->txlast = next_desc(port, port->txlast, 1);
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}
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netif_wake_queue(dev);
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spin_unlock(&port->lock);
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}
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static irqreturn_t sca_intr(int irq, void* dev_id)
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{
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card_t *card = dev_id;
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int i;
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u8 stat;
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int handled = 0;
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u8 page = sca_get_page(card);
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while((stat = sca_intr_status(card)) != 0) {
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handled = 1;
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for (i = 0; i < 2; i++) {
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port_t *port = get_port(card, i);
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if (port) {
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if (stat & SCA_INTR_MSCI(i))
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sca_msci_intr(port);
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if (stat & SCA_INTR_DMAC_RX(i))
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sca_rx_intr(port);
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if (stat & SCA_INTR_DMAC_TX(i))
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sca_tx_intr(port);
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}
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}
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}
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openwin(card, page); /* Restore original page */
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return IRQ_RETVAL(handled);
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}
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static void sca_set_port(port_t *port)
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{
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card_t* card = port_to_card(port);
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u16 msci = get_msci(port);
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u8 md2 = sca_in(msci + MD2, card);
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unsigned int tmc, br = 10, brv = 1024;
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if (port->settings.clock_rate > 0) {
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/* Try lower br for better accuracy*/
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do {
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br--;
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brv >>= 1; /* brv = 2^9 = 512 max in specs */
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/* Baud Rate = CLOCK_BASE / TMC / 2^BR */
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tmc = CLOCK_BASE / brv / port->settings.clock_rate;
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}while (br > 1 && tmc <= 128);
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if (tmc < 1) {
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tmc = 1;
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br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
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brv = 1;
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} else if (tmc > 255)
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tmc = 256; /* tmc=0 means 256 - low baud rates */
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port->settings.clock_rate = CLOCK_BASE / brv / tmc;
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} else {
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br = 9; /* Minimum clock rate */
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tmc = 256; /* 8bit = 0 */
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port->settings.clock_rate = CLOCK_BASE / (256 * 512);
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}
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port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
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port->txs = (port->txs & ~CLK_BRG_MASK) | br;
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port->tmc = tmc;
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/* baud divisor - time constant*/
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sca_out(port->tmc, msci + TMC, card);
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/* Set BRG bits */
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sca_out(port->rxs, msci + RXS, card);
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sca_out(port->txs, msci + TXS, card);
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if (port->settings.loopback)
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md2 |= MD2_LOOPBACK;
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else
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md2 &= ~MD2_LOOPBACK;
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sca_out(md2, msci + MD2, card);
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}
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static void sca_open(struct net_device *dev)
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{
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port_t *port = dev_to_port(dev);
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card_t* card = port_to_card(port);
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u16 msci = get_msci(port);
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u8 md0, md2;
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switch(port->encoding) {
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case ENCODING_NRZ: md2 = MD2_NRZ; break;
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case ENCODING_NRZI: md2 = MD2_NRZI; break;
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case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
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case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
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default: md2 = MD2_MANCHESTER;
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}
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if (port->settings.loopback)
|
|
md2 |= MD2_LOOPBACK;
|
|
|
|
switch(port->parity) {
|
|
case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
|
|
case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
|
|
case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
|
|
case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
|
|
default: md0 = MD0_HDLC | MD0_CRC_NONE;
|
|
}
|
|
|
|
sca_out(CMD_RESET, msci + CMD, card);
|
|
sca_out(md0, msci + MD0, card);
|
|
sca_out(0x00, msci + MD1, card); /* no address field check */
|
|
sca_out(md2, msci + MD2, card);
|
|
sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
|
|
sca_out(CTL_IDLE, msci + CTL, card);
|
|
|
|
/* Allow at least 8 bytes before requesting RX DMA operation */
|
|
/* TX with higher priority and possibly with shorter transfers */
|
|
sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
|
|
sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
|
|
sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
|
|
|
|
/* We're using the following interrupts:
|
|
- TXINT (DMAC completed all transmisions, underrun or DCD change)
|
|
- all DMA interrupts
|
|
*/
|
|
sca_set_carrier(port);
|
|
|
|
/* MSCI TX INT and RX INT A IRQ enable */
|
|
sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
|
|
sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
|
|
sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
|
|
IER0, card); /* TXINT and RXINT */
|
|
/* enable DMA IRQ */
|
|
sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
|
|
IER1, card);
|
|
|
|
sca_out(port->tmc, msci + TMC, card); /* Restore registers */
|
|
sca_out(port->rxs, msci + RXS, card);
|
|
sca_out(port->txs, msci + TXS, card);
|
|
sca_out(CMD_TX_ENABLE, msci + CMD, card);
|
|
sca_out(CMD_RX_ENABLE, msci + CMD, card);
|
|
|
|
netif_start_queue(dev);
|
|
}
|
|
|
|
|
|
static void sca_close(struct net_device *dev)
|
|
{
|
|
port_t *port = dev_to_port(dev);
|
|
card_t* card = port_to_card(port);
|
|
|
|
/* reset channel */
|
|
sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
|
|
/* disable MSCI interrupts */
|
|
sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
|
|
IER0, card);
|
|
/* disable DMA interrupts */
|
|
sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
|
|
IER1, card);
|
|
|
|
netif_stop_queue(dev);
|
|
}
|
|
|
|
|
|
static int sca_attach(struct net_device *dev, unsigned short encoding,
|
|
unsigned short parity)
|
|
{
|
|
if (encoding != ENCODING_NRZ &&
|
|
encoding != ENCODING_NRZI &&
|
|
encoding != ENCODING_FM_MARK &&
|
|
encoding != ENCODING_FM_SPACE &&
|
|
encoding != ENCODING_MANCHESTER)
|
|
return -EINVAL;
|
|
|
|
if (parity != PARITY_NONE &&
|
|
parity != PARITY_CRC16_PR0 &&
|
|
parity != PARITY_CRC16_PR1 &&
|
|
parity != PARITY_CRC16_PR0_CCITT &&
|
|
parity != PARITY_CRC16_PR1_CCITT)
|
|
return -EINVAL;
|
|
|
|
dev_to_port(dev)->encoding = encoding;
|
|
dev_to_port(dev)->parity = parity;
|
|
return 0;
|
|
}
|
|
|
|
|
|
#ifdef DEBUG_RINGS
|
|
static void sca_dump_rings(struct net_device *dev)
|
|
{
|
|
port_t *port = dev_to_port(dev);
|
|
card_t *card = port_to_card(port);
|
|
u16 cnt;
|
|
#ifndef PAGE0_ALWAYS_MAPPED
|
|
u8 page = sca_get_page(card);
|
|
|
|
openwin(card, 0);
|
|
#endif
|
|
|
|
printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
|
|
sca_inw(get_dmac_rx(port) + CDAL, card),
|
|
sca_inw(get_dmac_rx(port) + EDAL, card),
|
|
sca_in(DSR_RX(phy_node(port)), card), port->rxin,
|
|
sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
|
|
for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
|
|
pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
|
|
pr_cont("\n");
|
|
|
|
printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
|
|
"last=%u %sactive",
|
|
sca_inw(get_dmac_tx(port) + CDAL, card),
|
|
sca_inw(get_dmac_tx(port) + EDAL, card),
|
|
sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
|
|
sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
|
|
|
|
for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
|
|
pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
|
|
pr_cont("\n");
|
|
|
|
printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
|
|
" FST: %02x CST: %02x %02x\n",
|
|
sca_in(get_msci(port) + MD0, card),
|
|
sca_in(get_msci(port) + MD1, card),
|
|
sca_in(get_msci(port) + MD2, card),
|
|
sca_in(get_msci(port) + ST0, card),
|
|
sca_in(get_msci(port) + ST1, card),
|
|
sca_in(get_msci(port) + ST2, card),
|
|
sca_in(get_msci(port) + ST3, card),
|
|
sca_in(get_msci(port) + FST, card),
|
|
sca_in(get_msci(port) + CST0, card),
|
|
sca_in(get_msci(port) + CST1, card));
|
|
|
|
printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
|
|
sca_in(ISR1, card), sca_in(ISR2, card));
|
|
|
|
#ifndef PAGE0_ALWAYS_MAPPED
|
|
openwin(card, page); /* Restore original page */
|
|
#endif
|
|
}
|
|
#endif /* DEBUG_RINGS */
|
|
|
|
|
|
static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
port_t *port = dev_to_port(dev);
|
|
card_t *card = port_to_card(port);
|
|
pkt_desc __iomem *desc;
|
|
u32 buff, len;
|
|
u8 page;
|
|
u32 maxlen;
|
|
|
|
spin_lock_irq(&port->lock);
|
|
|
|
desc = desc_address(port, port->txin + 1, 1);
|
|
BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
|
|
|
|
#ifdef DEBUG_PKT
|
|
printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
|
|
debug_frame(skb);
|
|
#endif
|
|
|
|
desc = desc_address(port, port->txin, 1);
|
|
buff = buffer_offset(port, port->txin, 1);
|
|
len = skb->len;
|
|
page = buff / winsize(card);
|
|
buff = buff % winsize(card);
|
|
maxlen = winsize(card) - buff;
|
|
|
|
openwin(card, page);
|
|
if (len > maxlen) {
|
|
memcpy_toio(winbase(card) + buff, skb->data, maxlen);
|
|
openwin(card, page + 1);
|
|
memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
|
|
} else
|
|
memcpy_toio(winbase(card) + buff, skb->data, len);
|
|
|
|
#ifndef PAGE0_ALWAYS_MAPPED
|
|
openwin(card, 0); /* select pkt_desc table page back */
|
|
#endif
|
|
writew(len, &desc->len);
|
|
writeb(ST_TX_EOM, &desc->stat);
|
|
|
|
port->txin = next_desc(port, port->txin, 1);
|
|
sca_outw(desc_offset(port, port->txin, 1),
|
|
get_dmac_tx(port) + EDAL, card);
|
|
|
|
sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
|
|
|
|
desc = desc_address(port, port->txin + 1, 1);
|
|
if (readb(&desc->stat)) /* allow 1 packet gap */
|
|
netif_stop_queue(dev);
|
|
|
|
spin_unlock_irq(&port->lock);
|
|
|
|
dev_kfree_skb(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
|
|
#ifdef NEED_DETECT_RAM
|
|
static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
|
|
{
|
|
/* Round RAM size to 32 bits, fill from end to start */
|
|
u32 i = ramsize &= ~3;
|
|
u32 size = winsize(card);
|
|
|
|
openwin(card, (i - 4) / size); /* select last window */
|
|
|
|
do {
|
|
i -= 4;
|
|
if ((i + 4) % size == 0)
|
|
openwin(card, i / size);
|
|
writel(i ^ 0x12345678, rambase + i % size);
|
|
} while (i > 0);
|
|
|
|
for (i = 0; i < ramsize ; i += 4) {
|
|
if (i % size == 0)
|
|
openwin(card, i / size);
|
|
|
|
if (readl(rambase + i % size) != (i ^ 0x12345678))
|
|
break;
|
|
}
|
|
|
|
return i;
|
|
}
|
|
#endif /* NEED_DETECT_RAM */
|
|
|
|
|
|
static void sca_init(card_t *card, int wait_states)
|
|
{
|
|
sca_out(wait_states, WCRL, card); /* Wait Control */
|
|
sca_out(wait_states, WCRM, card);
|
|
sca_out(wait_states, WCRH, card);
|
|
|
|
sca_out(0, DMER, card); /* DMA Master disable */
|
|
sca_out(0x03, PCR, card); /* DMA priority */
|
|
sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
|
|
sca_out(0, DSR_TX(0), card);
|
|
sca_out(0, DSR_RX(1), card);
|
|
sca_out(0, DSR_TX(1), card);
|
|
sca_out(DMER_DME, DMER, card); /* DMA Master enable */
|
|
}
|