404 lines
18 KiB
C
404 lines
18 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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* Microsemi Ocelot Switch driver
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* Copyright (c) 2019 Microsemi Corporation
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*/
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#ifndef _OCELOT_VCAP_H_
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#define _OCELOT_VCAP_H_
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/* =================================================================
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* VCAP Common
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* =================================================================
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*/
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/* VCAP Type-Group values */
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#define VCAP_TG_NONE 0 /* Entry is invalid */
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#define VCAP_TG_FULL 1 /* Full entry */
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#define VCAP_TG_HALF 2 /* Half entry */
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#define VCAP_TG_QUARTER 3 /* Quarter entry */
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/* =================================================================
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* VCAP IS2
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* =================================================================
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*/
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#define VCAP_IS2_CNT 64
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#define VCAP_IS2_ENTRY_WIDTH 376
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#define VCAP_IS2_ACTION_WIDTH 99
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#define VCAP_PORT_CNT 11
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/* IS2 half key types */
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#define IS2_TYPE_ETYPE 0
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#define IS2_TYPE_LLC 1
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#define IS2_TYPE_SNAP 2
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#define IS2_TYPE_ARP 3
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#define IS2_TYPE_IP_UDP_TCP 4
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#define IS2_TYPE_IP_OTHER 5
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#define IS2_TYPE_IPV6 6
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#define IS2_TYPE_OAM 7
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#define IS2_TYPE_SMAC_SIP6 8
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#define IS2_TYPE_ANY 100 /* Pseudo type */
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/* IS2 half key type mask for matching any IP */
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#define IS2_TYPE_MASK_IP_ANY 0xe
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/* IS2 action types */
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#define IS2_ACTION_TYPE_NORMAL 0
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#define IS2_ACTION_TYPE_SMAC_SIP 1
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/* IS2 MASK_MODE values */
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#define IS2_ACT_MASK_MODE_NONE 0
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#define IS2_ACT_MASK_MODE_FILTER 1
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#define IS2_ACT_MASK_MODE_POLICY 2
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#define IS2_ACT_MASK_MODE_REDIR 3
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/* IS2 REW_OP values */
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#define IS2_ACT_REW_OP_NONE 0
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#define IS2_ACT_REW_OP_PTP_ONE 2
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#define IS2_ACT_REW_OP_PTP_TWO 3
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#define IS2_ACT_REW_OP_SPECIAL 8
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#define IS2_ACT_REW_OP_PTP_ORG 9
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#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
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#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
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#define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
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#define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
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#define VCAP_PORT_WIDTH 4
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/* IS2 quarter key - SMAC_SIP4 */
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#define IS2_QKO_IGR_PORT 0
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#define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
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#define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
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#define IS2_QKL_L2_SMAC 48
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#define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
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#define IS2_QKL_L3_IP4_SIP 32
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/* IS2 half key - common */
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#define IS2_HKO_TYPE 0
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#define IS2_HKL_TYPE 4
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#define IS2_HKO_FIRST (IS2_HKO_TYPE + IS2_HKL_TYPE)
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#define IS2_HKL_FIRST 1
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#define IS2_HKO_PAG (IS2_HKO_FIRST + IS2_HKL_FIRST)
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#define IS2_HKL_PAG 8
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#define IS2_HKO_IGR_PORT_MASK (IS2_HKO_PAG + IS2_HKL_PAG)
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#define IS2_HKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1)
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#define IS2_HKO_SERVICE_FRM (IS2_HKO_IGR_PORT_MASK + IS2_HKL_IGR_PORT_MASK)
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#define IS2_HKL_SERVICE_FRM 1
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#define IS2_HKO_HOST_MATCH (IS2_HKO_SERVICE_FRM + IS2_HKL_SERVICE_FRM)
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#define IS2_HKL_HOST_MATCH 1
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#define IS2_HKO_L2_MC (IS2_HKO_HOST_MATCH + IS2_HKL_HOST_MATCH)
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#define IS2_HKL_L2_MC 1
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#define IS2_HKO_L2_BC (IS2_HKO_L2_MC + IS2_HKL_L2_MC)
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#define IS2_HKL_L2_BC 1
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#define IS2_HKO_VLAN_TAGGED (IS2_HKO_L2_BC + IS2_HKL_L2_BC)
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#define IS2_HKL_VLAN_TAGGED 1
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#define IS2_HKO_VID (IS2_HKO_VLAN_TAGGED + IS2_HKL_VLAN_TAGGED)
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#define IS2_HKL_VID 12
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#define IS2_HKO_DEI (IS2_HKO_VID + IS2_HKL_VID)
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#define IS2_HKL_DEI 1
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#define IS2_HKO_PCP (IS2_HKO_DEI + IS2_HKL_DEI)
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#define IS2_HKL_PCP 3
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/* IS2 half key - MAC_ETYPE/MAC_LLC/MAC_SNAP/OAM common */
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#define IS2_HKO_L2_DMAC (IS2_HKO_PCP + IS2_HKL_PCP)
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#define IS2_HKL_L2_DMAC 48
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#define IS2_HKO_L2_SMAC (IS2_HKO_L2_DMAC + IS2_HKL_L2_DMAC)
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#define IS2_HKL_L2_SMAC 48
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/* IS2 half key - MAC_ETYPE */
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#define IS2_HKO_MAC_ETYPE_ETYPE (IS2_HKO_L2_SMAC + IS2_HKL_L2_SMAC)
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#define IS2_HKL_MAC_ETYPE_ETYPE 16
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#define IS2_HKO_MAC_ETYPE_L2_PAYLOAD \
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(IS2_HKO_MAC_ETYPE_ETYPE + IS2_HKL_MAC_ETYPE_ETYPE)
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#define IS2_HKL_MAC_ETYPE_L2_PAYLOAD 27
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/* IS2 half key - MAC_LLC */
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#define IS2_HKO_MAC_LLC_L2_LLC IS2_HKO_MAC_ETYPE_ETYPE
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#define IS2_HKL_MAC_LLC_L2_LLC 40
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/* IS2 half key - MAC_SNAP */
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#define IS2_HKO_MAC_SNAP_L2_SNAP IS2_HKO_MAC_ETYPE_ETYPE
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#define IS2_HKL_MAC_SNAP_L2_SNAP 40
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/* IS2 half key - ARP */
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#define IS2_HKO_MAC_ARP_L2_SMAC IS2_HKO_L2_DMAC
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#define IS2_HKL_MAC_ARP_L2_SMAC 48
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#define IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK \
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(IS2_HKO_MAC_ARP_L2_SMAC + IS2_HKL_MAC_ARP_L2_SMAC)
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#define IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK 1
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#define IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK \
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(IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK + IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK)
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#define IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK 1
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#define IS2_HKO_MAC_ARP_ARP_LEN_OK \
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(IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK + \
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IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK)
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#define IS2_HKL_MAC_ARP_ARP_LEN_OK 1
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#define IS2_HKO_MAC_ARP_ARP_TGT_MATCH \
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(IS2_HKO_MAC_ARP_ARP_LEN_OK + IS2_HKL_MAC_ARP_ARP_LEN_OK)
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#define IS2_HKL_MAC_ARP_ARP_TGT_MATCH 1
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#define IS2_HKO_MAC_ARP_ARP_SENDER_MATCH \
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(IS2_HKO_MAC_ARP_ARP_TGT_MATCH + IS2_HKL_MAC_ARP_ARP_TGT_MATCH)
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#define IS2_HKL_MAC_ARP_ARP_SENDER_MATCH 1
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#define IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN \
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(IS2_HKO_MAC_ARP_ARP_SENDER_MATCH + IS2_HKL_MAC_ARP_ARP_SENDER_MATCH)
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#define IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN 1
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#define IS2_HKO_MAC_ARP_ARP_OPCODE \
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(IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN + \
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IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN)
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#define IS2_HKL_MAC_ARP_ARP_OPCODE 2
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#define IS2_HKO_MAC_ARP_L3_IP4_DIP \
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(IS2_HKO_MAC_ARP_ARP_OPCODE + IS2_HKL_MAC_ARP_ARP_OPCODE)
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#define IS2_HKL_MAC_ARP_L3_IP4_DIP 32
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#define IS2_HKO_MAC_ARP_L3_IP4_SIP \
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(IS2_HKO_MAC_ARP_L3_IP4_DIP + IS2_HKL_MAC_ARP_L3_IP4_DIP)
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#define IS2_HKL_MAC_ARP_L3_IP4_SIP 32
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#define IS2_HKO_MAC_ARP_DIP_EQ_SIP \
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(IS2_HKO_MAC_ARP_L3_IP4_SIP + IS2_HKL_MAC_ARP_L3_IP4_SIP)
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#define IS2_HKL_MAC_ARP_DIP_EQ_SIP 1
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/* IS2 half key - IP4_TCP_UDP/IP4_OTHER common */
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#define IS2_HKO_IP4 IS2_HKO_L2_DMAC
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#define IS2_HKL_IP4 1
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#define IS2_HKO_L3_FRAGMENT (IS2_HKO_IP4 + IS2_HKL_IP4)
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#define IS2_HKL_L3_FRAGMENT 1
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#define IS2_HKO_L3_FRAG_OFS_GT0 (IS2_HKO_L3_FRAGMENT + IS2_HKL_L3_FRAGMENT)
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#define IS2_HKL_L3_FRAG_OFS_GT0 1
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#define IS2_HKO_L3_OPTIONS (IS2_HKO_L3_FRAG_OFS_GT0 + IS2_HKL_L3_FRAG_OFS_GT0)
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#define IS2_HKL_L3_OPTIONS 1
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#define IS2_HKO_L3_TTL_GT0 (IS2_HKO_L3_OPTIONS + IS2_HKL_L3_OPTIONS)
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#define IS2_HKL_L3_TTL_GT0 1
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#define IS2_HKO_L3_TOS (IS2_HKO_L3_TTL_GT0 + IS2_HKL_L3_TTL_GT0)
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#define IS2_HKL_L3_TOS 8
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#define IS2_HKO_L3_IP4_DIP (IS2_HKO_L3_TOS + IS2_HKL_L3_TOS)
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#define IS2_HKL_L3_IP4_DIP 32
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#define IS2_HKO_L3_IP4_SIP (IS2_HKO_L3_IP4_DIP + IS2_HKL_L3_IP4_DIP)
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#define IS2_HKL_L3_IP4_SIP 32
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#define IS2_HKO_DIP_EQ_SIP (IS2_HKO_L3_IP4_SIP + IS2_HKL_L3_IP4_SIP)
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#define IS2_HKL_DIP_EQ_SIP 1
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/* IS2 half key - IP4_TCP_UDP */
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#define IS2_HKO_IP4_TCP_UDP_TCP (IS2_HKO_DIP_EQ_SIP + IS2_HKL_DIP_EQ_SIP)
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#define IS2_HKL_IP4_TCP_UDP_TCP 1
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#define IS2_HKO_IP4_TCP_UDP_L4_DPORT \
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(IS2_HKO_IP4_TCP_UDP_TCP + IS2_HKL_IP4_TCP_UDP_TCP)
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#define IS2_HKL_IP4_TCP_UDP_L4_DPORT 16
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#define IS2_HKO_IP4_TCP_UDP_L4_SPORT \
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(IS2_HKO_IP4_TCP_UDP_L4_DPORT + IS2_HKL_IP4_TCP_UDP_L4_DPORT)
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#define IS2_HKL_IP4_TCP_UDP_L4_SPORT 16
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#define IS2_HKO_IP4_TCP_UDP_L4_RNG \
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(IS2_HKO_IP4_TCP_UDP_L4_SPORT + IS2_HKL_IP4_TCP_UDP_L4_SPORT)
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#define IS2_HKL_IP4_TCP_UDP_L4_RNG 8
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#define IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT \
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(IS2_HKO_IP4_TCP_UDP_L4_RNG + IS2_HKL_IP4_TCP_UDP_L4_RNG)
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#define IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT 1
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#define IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 \
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(IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT + \
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IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT)
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#define IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0 1
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#define IS2_HKO_IP4_TCP_UDP_L4_FIN \
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(IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 + IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0)
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#define IS2_HKL_IP4_TCP_UDP_L4_FIN 1
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#define IS2_HKO_IP4_TCP_UDP_L4_SYN \
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(IS2_HKO_IP4_TCP_UDP_L4_FIN + IS2_HKL_IP4_TCP_UDP_L4_FIN)
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#define IS2_HKL_IP4_TCP_UDP_L4_SYN 1
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#define IS2_HKO_IP4_TCP_UDP_L4_RST \
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(IS2_HKO_IP4_TCP_UDP_L4_SYN + IS2_HKL_IP4_TCP_UDP_L4_SYN)
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#define IS2_HKL_IP4_TCP_UDP_L4_RST 1
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#define IS2_HKO_IP4_TCP_UDP_L4_PSH \
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(IS2_HKO_IP4_TCP_UDP_L4_RST + IS2_HKL_IP4_TCP_UDP_L4_RST)
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#define IS2_HKL_IP4_TCP_UDP_L4_PSH 1
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#define IS2_HKO_IP4_TCP_UDP_L4_ACK \
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(IS2_HKO_IP4_TCP_UDP_L4_PSH + IS2_HKL_IP4_TCP_UDP_L4_PSH)
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#define IS2_HKL_IP4_TCP_UDP_L4_ACK 1
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#define IS2_HKO_IP4_TCP_UDP_L4_URG \
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(IS2_HKO_IP4_TCP_UDP_L4_ACK + IS2_HKL_IP4_TCP_UDP_L4_ACK)
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#define IS2_HKL_IP4_TCP_UDP_L4_URG 1
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#define IS2_HKO_IP4_TCP_UDP_L4_1588_DOM \
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(IS2_HKO_IP4_TCP_UDP_L4_URG + IS2_HKL_IP4_TCP_UDP_L4_URG)
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#define IS2_HKL_IP4_TCP_UDP_L4_1588_DOM 8
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#define IS2_HKO_IP4_TCP_UDP_L4_1588_VER \
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(IS2_HKO_IP4_TCP_UDP_L4_1588_DOM + IS2_HKL_IP4_TCP_UDP_L4_1588_DOM)
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#define IS2_HKL_IP4_TCP_UDP_L4_1588_VER 4
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/* IS2 half key - IP4_OTHER */
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#define IS2_HKO_IP4_OTHER_L3_PROTO IS2_HKO_IP4_TCP_UDP_TCP
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#define IS2_HKL_IP4_OTHER_L3_PROTO 8
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#define IS2_HKO_IP4_OTHER_L3_PAYLOAD \
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(IS2_HKO_IP4_OTHER_L3_PROTO + IS2_HKL_IP4_OTHER_L3_PROTO)
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#define IS2_HKL_IP4_OTHER_L3_PAYLOAD 56
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/* IS2 half key - IP6_STD */
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#define IS2_HKO_IP6_STD_L3_TTL_GT0 IS2_HKO_L2_DMAC
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#define IS2_HKL_IP6_STD_L3_TTL_GT0 1
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#define IS2_HKO_IP6_STD_L3_IP6_SIP \
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(IS2_HKO_IP6_STD_L3_TTL_GT0 + IS2_HKL_IP6_STD_L3_TTL_GT0)
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#define IS2_HKL_IP6_STD_L3_IP6_SIP 128
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#define IS2_HKO_IP6_STD_L3_PROTO \
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(IS2_HKO_IP6_STD_L3_IP6_SIP + IS2_HKL_IP6_STD_L3_IP6_SIP)
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#define IS2_HKL_IP6_STD_L3_PROTO 8
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/* IS2 half key - OAM */
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#define IS2_HKO_OAM_OAM_MEL_FLAGS IS2_HKO_MAC_ETYPE_ETYPE
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#define IS2_HKL_OAM_OAM_MEL_FLAGS 7
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#define IS2_HKO_OAM_OAM_VER \
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(IS2_HKO_OAM_OAM_MEL_FLAGS + IS2_HKL_OAM_OAM_MEL_FLAGS)
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#define IS2_HKL_OAM_OAM_VER 5
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#define IS2_HKO_OAM_OAM_OPCODE (IS2_HKO_OAM_OAM_VER + IS2_HKL_OAM_OAM_VER)
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#define IS2_HKL_OAM_OAM_OPCODE 8
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#define IS2_HKO_OAM_OAM_FLAGS (IS2_HKO_OAM_OAM_OPCODE + IS2_HKL_OAM_OAM_OPCODE)
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#define IS2_HKL_OAM_OAM_FLAGS 8
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#define IS2_HKO_OAM_OAM_MEPID (IS2_HKO_OAM_OAM_FLAGS + IS2_HKL_OAM_OAM_FLAGS)
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#define IS2_HKL_OAM_OAM_MEPID 16
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#define IS2_HKO_OAM_OAM_CCM_CNTS_EQ0 \
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(IS2_HKO_OAM_OAM_MEPID + IS2_HKL_OAM_OAM_MEPID)
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#define IS2_HKL_OAM_OAM_CCM_CNTS_EQ0 1
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/* IS2 half key - SMAC_SIP6 */
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#define IS2_HKO_SMAC_SIP6_IGR_PORT IS2_HKL_TYPE
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#define IS2_HKL_SMAC_SIP6_IGR_PORT VCAP_PORT_WIDTH
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#define IS2_HKO_SMAC_SIP6_L2_SMAC \
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(IS2_HKO_SMAC_SIP6_IGR_PORT + IS2_HKL_SMAC_SIP6_IGR_PORT)
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#define IS2_HKL_SMAC_SIP6_L2_SMAC 48
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#define IS2_HKO_SMAC_SIP6_L3_IP6_SIP \
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(IS2_HKO_SMAC_SIP6_L2_SMAC + IS2_HKL_SMAC_SIP6_L2_SMAC)
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#define IS2_HKL_SMAC_SIP6_L3_IP6_SIP 128
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/* IS2 full key - common */
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#define IS2_FKO_TYPE 0
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#define IS2_FKL_TYPE 2
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#define IS2_FKO_FIRST (IS2_FKO_TYPE + IS2_FKL_TYPE)
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#define IS2_FKL_FIRST 1
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#define IS2_FKO_PAG (IS2_FKO_FIRST + IS2_FKL_FIRST)
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#define IS2_FKL_PAG 8
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#define IS2_FKO_IGR_PORT_MASK (IS2_FKO_PAG + IS2_FKL_PAG)
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#define IS2_FKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1)
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#define IS2_FKO_SERVICE_FRM (IS2_FKO_IGR_PORT_MASK + IS2_FKL_IGR_PORT_MASK)
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#define IS2_FKL_SERVICE_FRM 1
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#define IS2_FKO_HOST_MATCH (IS2_FKO_SERVICE_FRM + IS2_FKL_SERVICE_FRM)
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#define IS2_FKL_HOST_MATCH 1
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#define IS2_FKO_L2_MC (IS2_FKO_HOST_MATCH + IS2_FKL_HOST_MATCH)
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#define IS2_FKL_L2_MC 1
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#define IS2_FKO_L2_BC (IS2_FKO_L2_MC + IS2_FKL_L2_MC)
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#define IS2_FKL_L2_BC 1
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#define IS2_FKO_VLAN_TAGGED (IS2_FKO_L2_BC + IS2_FKL_L2_BC)
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#define IS2_FKL_VLAN_TAGGED 1
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#define IS2_FKO_VID (IS2_FKO_VLAN_TAGGED + IS2_FKL_VLAN_TAGGED)
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#define IS2_FKL_VID 12
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#define IS2_FKO_DEI (IS2_FKO_VID + IS2_FKL_VID)
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#define IS2_FKL_DEI 1
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#define IS2_FKO_PCP (IS2_FKO_DEI + IS2_FKL_DEI)
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#define IS2_FKL_PCP 3
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/* IS2 full key - IP6_TCP_UDP/IP6_OTHER common */
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#define IS2_FKO_L3_TTL_GT0 (IS2_FKO_PCP + IS2_FKL_PCP)
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#define IS2_FKL_L3_TTL_GT0 1
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#define IS2_FKO_L3_TOS (IS2_FKO_L3_TTL_GT0 + IS2_FKL_L3_TTL_GT0)
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#define IS2_FKL_L3_TOS 8
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#define IS2_FKO_L3_IP6_DIP (IS2_FKO_L3_TOS + IS2_FKL_L3_TOS)
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#define IS2_FKL_L3_IP6_DIP 128
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#define IS2_FKO_L3_IP6_SIP (IS2_FKO_L3_IP6_DIP + IS2_FKL_L3_IP6_DIP)
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#define IS2_FKL_L3_IP6_SIP 128
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#define IS2_FKO_DIP_EQ_SIP (IS2_FKO_L3_IP6_SIP + IS2_FKL_L3_IP6_SIP)
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#define IS2_FKL_DIP_EQ_SIP 1
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/* IS2 full key - IP6_TCP_UDP */
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#define IS2_FKO_IP6_TCP_UDP_TCP (IS2_FKO_DIP_EQ_SIP + IS2_FKL_DIP_EQ_SIP)
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#define IS2_FKL_IP6_TCP_UDP_TCP 1
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#define IS2_FKO_IP6_TCP_UDP_L4_DPORT \
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(IS2_FKO_IP6_TCP_UDP_TCP + IS2_FKL_IP6_TCP_UDP_TCP)
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#define IS2_FKL_IP6_TCP_UDP_L4_DPORT 16
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#define IS2_FKO_IP6_TCP_UDP_L4_SPORT \
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(IS2_FKO_IP6_TCP_UDP_L4_DPORT + IS2_FKL_IP6_TCP_UDP_L4_DPORT)
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#define IS2_FKL_IP6_TCP_UDP_L4_SPORT 16
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#define IS2_FKO_IP6_TCP_UDP_L4_RNG \
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(IS2_FKO_IP6_TCP_UDP_L4_SPORT + IS2_FKL_IP6_TCP_UDP_L4_SPORT)
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#define IS2_FKL_IP6_TCP_UDP_L4_RNG 8
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#define IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT \
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(IS2_FKO_IP6_TCP_UDP_L4_RNG + IS2_FKL_IP6_TCP_UDP_L4_RNG)
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#define IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT 1
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#define IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 \
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(IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT + \
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IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT)
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#define IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0 1
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#define IS2_FKO_IP6_TCP_UDP_L4_FIN \
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(IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 + IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0)
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#define IS2_FKL_IP6_TCP_UDP_L4_FIN 1
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#define IS2_FKO_IP6_TCP_UDP_L4_SYN \
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(IS2_FKO_IP6_TCP_UDP_L4_FIN + IS2_FKL_IP6_TCP_UDP_L4_FIN)
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#define IS2_FKL_IP6_TCP_UDP_L4_SYN 1
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#define IS2_FKO_IP6_TCP_UDP_L4_RST \
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(IS2_FKO_IP6_TCP_UDP_L4_SYN + IS2_FKL_IP6_TCP_UDP_L4_SYN)
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#define IS2_FKL_IP6_TCP_UDP_L4_RST 1
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#define IS2_FKO_IP6_TCP_UDP_L4_PSH \
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(IS2_FKO_IP6_TCP_UDP_L4_RST + IS2_FKL_IP6_TCP_UDP_L4_RST)
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#define IS2_FKL_IP6_TCP_UDP_L4_PSH 1
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#define IS2_FKO_IP6_TCP_UDP_L4_ACK \
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(IS2_FKO_IP6_TCP_UDP_L4_PSH + IS2_FKL_IP6_TCP_UDP_L4_PSH)
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#define IS2_FKL_IP6_TCP_UDP_L4_ACK 1
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#define IS2_FKO_IP6_TCP_UDP_L4_URG \
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(IS2_FKO_IP6_TCP_UDP_L4_ACK + IS2_FKL_IP6_TCP_UDP_L4_ACK)
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#define IS2_FKL_IP6_TCP_UDP_L4_URG 1
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#define IS2_FKO_IP6_TCP_UDP_L4_1588_DOM \
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(IS2_FKO_IP6_TCP_UDP_L4_URG + IS2_FKL_IP6_TCP_UDP_L4_URG)
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#define IS2_FKL_IP6_TCP_UDP_L4_1588_DOM 8
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#define IS2_FKO_IP6_TCP_UDP_L4_1588_VER \
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(IS2_FKO_IP6_TCP_UDP_L4_1588_DOM + IS2_FKL_IP6_TCP_UDP_L4_1588_DOM)
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#define IS2_FKL_IP6_TCP_UDP_L4_1588_VER 4
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/* IS2 full key - IP6_OTHER */
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#define IS2_FKO_IP6_OTHER_L3_PROTO IS2_FKO_IP6_TCP_UDP_TCP
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#define IS2_FKL_IP6_OTHER_L3_PROTO 8
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#define IS2_FKO_IP6_OTHER_L3_PAYLOAD \
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(IS2_FKO_IP6_OTHER_L3_PROTO + IS2_FKL_IP6_OTHER_L3_PROTO)
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#define IS2_FKL_IP6_OTHER_L3_PAYLOAD 56
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/* IS2 full key - CUSTOM */
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#define IS2_FKO_CUSTOM_CUSTOM_TYPE IS2_FKO_L3_TTL_GT0
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#define IS2_FKL_CUSTOM_CUSTOM_TYPE 1
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#define IS2_FKO_CUSTOM_CUSTOM \
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(IS2_FKO_CUSTOM_CUSTOM_TYPE + IS2_FKL_CUSTOM_CUSTOM_TYPE)
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#define IS2_FKL_CUSTOM_CUSTOM 320
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/* IS2 action - BASE_TYPE */
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#define IS2_AO_HIT_ME_ONCE 0
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#define IS2_AL_HIT_ME_ONCE 1
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#define IS2_AO_CPU_COPY_ENA (IS2_AO_HIT_ME_ONCE + IS2_AL_HIT_ME_ONCE)
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#define IS2_AL_CPU_COPY_ENA 1
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#define IS2_AO_CPU_QU_NUM (IS2_AO_CPU_COPY_ENA + IS2_AL_CPU_COPY_ENA)
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#define IS2_AL_CPU_QU_NUM 3
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#define IS2_AO_MASK_MODE (IS2_AO_CPU_QU_NUM + IS2_AL_CPU_QU_NUM)
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#define IS2_AL_MASK_MODE 2
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#define IS2_AO_MIRROR_ENA (IS2_AO_MASK_MODE + IS2_AL_MASK_MODE)
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#define IS2_AL_MIRROR_ENA 1
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#define IS2_AO_LRN_DIS (IS2_AO_MIRROR_ENA + IS2_AL_MIRROR_ENA)
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#define IS2_AL_LRN_DIS 1
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#define IS2_AO_POLICE_ENA (IS2_AO_LRN_DIS + IS2_AL_LRN_DIS)
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#define IS2_AL_POLICE_ENA 1
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#define IS2_AO_POLICE_IDX (IS2_AO_POLICE_ENA + IS2_AL_POLICE_ENA)
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#define IS2_AL_POLICE_IDX 9
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#define IS2_AO_POLICE_VCAP_ONLY (IS2_AO_POLICE_IDX + IS2_AL_POLICE_IDX)
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#define IS2_AL_POLICE_VCAP_ONLY 1
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#define IS2_AO_PORT_MASK (IS2_AO_POLICE_VCAP_ONLY + IS2_AL_POLICE_VCAP_ONLY)
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#define IS2_AL_PORT_MASK VCAP_PORT_CNT
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#define IS2_AO_REW_OP (IS2_AO_PORT_MASK + IS2_AL_PORT_MASK)
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#define IS2_AL_REW_OP 9
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#define IS2_AO_LM_CNT_DIS (IS2_AO_REW_OP + IS2_AL_REW_OP)
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#define IS2_AL_LM_CNT_DIS 1
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#define IS2_AO_ISDX_ENA \
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(IS2_AO_LM_CNT_DIS + IS2_AL_LM_CNT_DIS + 1) /* Reserved bit */
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#define IS2_AL_ISDX_ENA 1
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#define IS2_AO_ACL_ID (IS2_AO_ISDX_ENA + IS2_AL_ISDX_ENA)
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#define IS2_AL_ACL_ID 6
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/* IS2 action - SMAC_SIP */
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#define IS2_AO_SMAC_SIP_CPU_COPY_ENA 0
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#define IS2_AL_SMAC_SIP_CPU_COPY_ENA 1
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#define IS2_AO_SMAC_SIP_CPU_QU_NUM 1
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#define IS2_AL_SMAC_SIP_CPU_QU_NUM 3
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#define IS2_AO_SMAC_SIP_FWD_KILL_ENA 4
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#define IS2_AL_SMAC_SIP_FWD_KILL_ENA 1
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#define IS2_AO_SMAC_SIP_HOST_MATCH 5
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#define IS2_AL_SMAC_SIP_HOST_MATCH 1
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#endif /* _OCELOT_VCAP_H_ */
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