548 lines
13 KiB
C
548 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Marvell 88E6xxx Switch Global (1) Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*/
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#include <linux/bitfield.h>
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#include "chip.h"
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#include "global1.h"
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int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
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bit, int val)
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{
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return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
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bit, val);
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}
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int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
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u16 mask, u16 val)
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{
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return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
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mask, val);
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}
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/* Offset 0x00: Switch Global Status Register */
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static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
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MV88E6185_G1_STS_PPU_STATE_MASK,
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MV88E6185_G1_STS_PPU_STATE_DISABLED);
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}
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static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
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MV88E6185_G1_STS_PPU_STATE_MASK,
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MV88E6185_G1_STS_PPU_STATE_POLLING);
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}
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static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
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{
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int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
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return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
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}
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static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
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{
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int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
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/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
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* is set to a one when all units inside the device (ATU, VTU, etc.)
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* have finished their initialization and are ready to accept frames.
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*/
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return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
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}
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/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
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* Offset 0x02: Switch MAC Address Register Bytes 2 & 3
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* Offset 0x03: Switch MAC Address Register Bytes 4 & 5
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*/
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int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
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{
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u16 reg;
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int err;
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reg = (addr[0] << 8) | addr[1];
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
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if (err)
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return err;
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reg = (addr[2] << 8) | addr[3];
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
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if (err)
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return err;
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reg = (addr[4] << 8) | addr[5];
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
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if (err)
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return err;
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return 0;
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}
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/* Offset 0x04: Switch Global Control Register */
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int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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/* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
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* the PPU, including re-doing PHY detection and initialization
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*/
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL1_SW_RESET;
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val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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err = mv88e6xxx_g1_wait_init_ready(chip);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_polling(chip);
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}
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int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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/* Set the SWReset bit 15 */
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL1_SW_RESET;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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return mv88e6xxx_g1_wait_init_ready(chip);
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}
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int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
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{
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int err;
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err = mv88e6250_g1_reset(chip);
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if (err)
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return err;
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return mv88e6352_g1_wait_ppu_polling(chip);
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}
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int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_polling(chip);
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}
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int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_disabled(chip);
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}
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/* Offset 0x10: IP-PRI Mapping Register 0
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* Offset 0x11: IP-PRI Mapping Register 1
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* Offset 0x12: IP-PRI Mapping Register 2
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* Offset 0x13: IP-PRI Mapping Register 3
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* Offset 0x14: IP-PRI Mapping Register 4
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* Offset 0x15: IP-PRI Mapping Register 5
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* Offset 0x16: IP-PRI Mapping Register 6
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* Offset 0x17: IP-PRI Mapping Register 7
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*/
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int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
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{
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int err;
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/* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
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if (err)
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return err;
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return 0;
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}
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/* Offset 0x18: IEEE-PRI Register */
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int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
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{
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/* Reset the IEEE Tag priorities to defaults */
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return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
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}
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int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
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{
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/* Reset the IEEE Tag priorities to defaults */
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return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
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}
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/* Offset 0x1a: Monitor Control */
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/* Offset 0x1a: Monitor & MGMT Control on some devices */
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int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
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if (err)
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return err;
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reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
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MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
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port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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/* Older generations also call this the ARP destination. It has been
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* generalized in more modern devices such that more than ARP can
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* egress it
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*/
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int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
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if (err)
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return err;
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reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
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reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
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u16 pointer, u8 data)
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{
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u16 reg;
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reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
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return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
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}
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int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 ptr;
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int err;
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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return 0;
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}
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int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
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{
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u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
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/* Use the default high priority for management frames sent to
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* the CPU.
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*/
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port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
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return mv88e6390_g1_monitor_write(chip, ptr, port);
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}
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int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
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{
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u16 ptr;
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int err;
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/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
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ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
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err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
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if (err)
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return err;
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return 0;
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}
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/* Offset 0x1c: Global Control 2 */
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static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
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u16 val)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
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if (err)
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return err;
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reg &= ~mask;
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reg |= val & mask;
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return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
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}
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int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
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{
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const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
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return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
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}
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int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
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MV88E6085_G1_CTL2_RM_ENABLE, 0);
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}
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int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
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MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
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}
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int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
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MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
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}
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int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
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MV88E6390_G1_CTL2_HIST_MODE_RX |
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MV88E6390_G1_CTL2_HIST_MODE_TX);
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}
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int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
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{
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return mv88e6xxx_g1_ctl2_mask(chip,
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MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
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index);
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}
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/* Offset 0x1d: Statistics Operation 2 */
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static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
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{
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int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
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return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
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}
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int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
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if (err)
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return err;
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val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
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return err;
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}
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int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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int err;
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|
|
|
/* Snapshot the hardware statistics counters for this port. */
|
|
err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
|
|
MV88E6XXX_G1_STATS_OP_BUSY |
|
|
MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
|
|
MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Wait for the snapshotting to complete. */
|
|
return mv88e6xxx_g1_stats_wait(chip);
|
|
}
|
|
|
|
int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
port = (port + 1) << 5;
|
|
|
|
return mv88e6xxx_g1_stats_snapshot(chip, port);
|
|
}
|
|
|
|
int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
int err;
|
|
|
|
port = (port + 1) << 5;
|
|
|
|
/* Snapshot the hardware statistics counters for this port. */
|
|
err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
|
|
MV88E6XXX_G1_STATS_OP_BUSY |
|
|
MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Wait for the snapshotting to complete. */
|
|
return mv88e6xxx_g1_stats_wait(chip);
|
|
}
|
|
|
|
void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
|
|
{
|
|
u32 value;
|
|
u16 reg;
|
|
int err;
|
|
|
|
*val = 0;
|
|
|
|
err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
|
|
MV88E6XXX_G1_STATS_OP_BUSY |
|
|
MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
|
|
if (err)
|
|
return;
|
|
|
|
err = mv88e6xxx_g1_stats_wait(chip);
|
|
if (err)
|
|
return;
|
|
|
|
err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
|
|
if (err)
|
|
return;
|
|
|
|
value = reg << 16;
|
|
|
|
err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
|
|
if (err)
|
|
return;
|
|
|
|
*val = value | reg;
|
|
}
|
|
|
|
int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
|
|
{
|
|
int err;
|
|
u16 val;
|
|
|
|
err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Keep the histogram mode bits */
|
|
val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
|
|
val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
|
|
|
|
err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Wait for the flush to complete. */
|
|
return mv88e6xxx_g1_stats_wait(chip);
|
|
}
|