370 lines
10 KiB
C
370 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// max8997-irq.c - Interrupt controller support for MAX8997
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//
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// Copyright (C) 2011 Samsung Electronics Co.Ltd
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// MyungJoo Ham <myungjoo.ham@samsung.com>
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//
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// This driver is based on max8998-irq.c
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/max8997.h>
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#include <linux/mfd/max8997-private.h>
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static const u8 max8997_mask_reg[] = {
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[PMIC_INT1] = MAX8997_REG_INT1MSK,
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[PMIC_INT2] = MAX8997_REG_INT2MSK,
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[PMIC_INT3] = MAX8997_REG_INT3MSK,
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[PMIC_INT4] = MAX8997_REG_INT4MSK,
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[FUEL_GAUGE] = MAX8997_REG_INVALID,
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[MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
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[MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
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[MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
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[GPIO_LOW] = MAX8997_REG_INVALID,
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[GPIO_HI] = MAX8997_REG_INVALID,
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[FLASH_STATUS] = MAX8997_REG_INVALID,
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};
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static struct i2c_client *get_i2c(struct max8997_dev *max8997,
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enum max8997_irq_source src)
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{
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switch (src) {
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case PMIC_INT1 ... PMIC_INT4:
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return max8997->i2c;
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case FUEL_GAUGE:
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return NULL;
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case MUIC_INT1 ... MUIC_INT3:
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return max8997->muic;
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case GPIO_LOW ... GPIO_HI:
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return max8997->i2c;
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case FLASH_STATUS:
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return max8997->i2c;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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struct max8997_irq_data {
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int mask;
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enum max8997_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct max8997_irq_data max8997_irqs[] = {
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DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0),
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DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1),
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DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3),
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DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4),
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DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5),
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DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6),
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DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7),
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DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0),
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DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1),
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DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2),
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DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3),
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DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4),
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DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5),
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DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
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DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0),
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DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1),
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DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2),
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DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3),
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DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5),
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DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7),
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DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0),
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DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1),
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DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2),
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DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3),
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DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4),
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DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5),
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DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2),
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DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1),
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DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0),
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DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4),
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DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3),
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DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2),
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DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1),
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DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0),
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DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2),
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};
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static void max8997_irq_lock(struct irq_data *data)
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{
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struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
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mutex_lock(&max8997->irqlock);
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}
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static void max8997_irq_sync_unlock(struct irq_data *data)
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{
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struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
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int i;
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for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
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u8 mask_reg = max8997_mask_reg[i];
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struct i2c_client *i2c = get_i2c(max8997, i);
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if (mask_reg == MAX8997_REG_INVALID ||
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IS_ERR_OR_NULL(i2c))
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continue;
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max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
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max8997_write_reg(i2c, max8997_mask_reg[i],
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max8997->irq_masks_cur[i]);
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}
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mutex_unlock(&max8997->irqlock);
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}
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inline static const struct max8997_irq_data *
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irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data)
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{
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return &max8997_irqs[data->hwirq];
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}
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static void max8997_irq_mask(struct irq_data *data)
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{
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struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
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const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
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data);
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max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void max8997_irq_unmask(struct irq_data *data)
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{
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struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
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const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
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data);
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max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip max8997_irq_chip = {
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.name = "max8997",
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.irq_bus_lock = max8997_irq_lock,
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.irq_bus_sync_unlock = max8997_irq_sync_unlock,
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.irq_mask = max8997_irq_mask,
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.irq_unmask = max8997_irq_unmask,
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};
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#define MAX8997_IRQSRC_PMIC (1 << 1)
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#define MAX8997_IRQSRC_FUELGAUGE (1 << 2)
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#define MAX8997_IRQSRC_MUIC (1 << 3)
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#define MAX8997_IRQSRC_GPIO (1 << 4)
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#define MAX8997_IRQSRC_FLASH (1 << 5)
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static irqreturn_t max8997_irq_thread(int irq, void *data)
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{
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struct max8997_dev *max8997 = data;
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u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
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u8 irq_src;
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int ret;
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int i, cur_irq;
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ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
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if (ret < 0) {
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dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
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ret);
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return IRQ_NONE;
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}
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if (irq_src & MAX8997_IRQSRC_PMIC) {
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/* PMIC INT1 ~ INT4 */
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max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
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&irq_reg[PMIC_INT1]);
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}
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if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
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/*
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* TODO: FUEL GAUGE
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*
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* This is to be supported by Max17042 driver. When
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* an interrupt incurs here, it should be relayed to a
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* Max17042 device that is connected (probably by
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* platform-data). However, we do not have interrupt
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* handling in Max17042 driver currently. The Max17042 IRQ
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* driver should be ready to be used as a stand-alone device and
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* a Max8997-dependent device. Because it is not ready in
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* Max17042-side and it is not too critical in operating
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* Max8997, we do not implement this in initial releases.
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*/
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irq_reg[FUEL_GAUGE] = 0;
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}
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if (irq_src & MAX8997_IRQSRC_MUIC) {
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/* MUIC INT1 ~ INT3 */
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max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
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&irq_reg[MUIC_INT1]);
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}
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if (irq_src & MAX8997_IRQSRC_GPIO) {
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/* GPIO Interrupt */
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u8 gpio_info[MAX8997_NUM_GPIO];
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irq_reg[GPIO_LOW] = 0;
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irq_reg[GPIO_HI] = 0;
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max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
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MAX8997_NUM_GPIO, gpio_info);
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for (i = 0; i < MAX8997_NUM_GPIO; i++) {
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bool interrupt = false;
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switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
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case MAX8997_GPIO_INT_BOTH:
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if (max8997->gpio_status[i] != gpio_info[i])
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interrupt = true;
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break;
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case MAX8997_GPIO_INT_RISE:
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if ((max8997->gpio_status[i] != gpio_info[i]) &&
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(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
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interrupt = true;
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break;
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case MAX8997_GPIO_INT_FALL:
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if ((max8997->gpio_status[i] != gpio_info[i]) &&
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!(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
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interrupt = true;
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break;
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default:
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break;
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}
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if (interrupt) {
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if (i < 8)
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irq_reg[GPIO_LOW] |= (1 << i);
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else
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irq_reg[GPIO_HI] |= (1 << (i - 8));
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}
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}
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}
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if (irq_src & MAX8997_IRQSRC_FLASH) {
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/* Flash Status Interrupt */
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ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
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&irq_reg[FLASH_STATUS]);
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}
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/* Apply masking */
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for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
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irq_reg[i] &= ~max8997->irq_masks_cur[i];
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/* Report */
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for (i = 0; i < MAX8997_IRQ_NR; i++) {
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if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
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cur_irq = irq_find_mapping(max8997->irq_domain, i);
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if (cur_irq)
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handle_nested_irq(cur_irq);
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}
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}
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return IRQ_HANDLED;
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}
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int max8997_irq_resume(struct max8997_dev *max8997)
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{
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if (max8997->irq && max8997->irq_domain)
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max8997_irq_thread(0, max8997);
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return 0;
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}
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static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct max8997_dev *max8997 = d->host_data;
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irq_set_chip_data(irq, max8997);
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irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
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irq_set_nested_thread(irq, 1);
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irq_set_noprobe(irq);
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return 0;
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}
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static const struct irq_domain_ops max8997_irq_domain_ops = {
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.map = max8997_irq_domain_map,
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};
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int max8997_irq_init(struct max8997_dev *max8997)
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{
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struct irq_domain *domain;
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int i;
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int ret;
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u8 val;
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if (!max8997->irq) {
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dev_warn(max8997->dev, "No interrupt specified.\n");
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return 0;
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}
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mutex_init(&max8997->irqlock);
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/* Mask individual interrupt sources */
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for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
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struct i2c_client *i2c;
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max8997->irq_masks_cur[i] = 0xff;
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max8997->irq_masks_cache[i] = 0xff;
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i2c = get_i2c(max8997, i);
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if (IS_ERR_OR_NULL(i2c))
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continue;
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if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
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continue;
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max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
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}
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for (i = 0; i < MAX8997_NUM_GPIO; i++) {
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max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
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MAX8997_REG_GPIOCNTL1 + i,
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&val)
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& MAX8997_GPIO_DATA_MASK) ?
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true : false;
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}
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domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
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&max8997_irq_domain_ops, max8997);
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if (!domain) {
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dev_err(max8997->dev, "could not create irq domain\n");
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return -ENODEV;
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}
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max8997->irq_domain = domain;
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ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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"max8997-irq", max8997);
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if (ret) {
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dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
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max8997->irq, ret);
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return ret;
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}
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if (!max8997->ono)
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return 0;
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ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
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IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
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IRQF_ONESHOT, "max8997-ono", max8997);
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if (ret)
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dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
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max8997->ono, ret);
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return 0;
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}
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void max8997_irq_exit(struct max8997_dev *max8997)
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{
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if (max8997->ono)
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free_irq(max8997->ono, max8997);
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if (max8997->irq)
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free_irq(max8997->irq, max8997);
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}
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