858 lines
22 KiB
C
858 lines
22 KiB
C
/*
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* (C) Copyright 2003-2004
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* Humboldt Solutions Ltd, adrian@humboldt.co.uk.
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* This is a combined i2c adapter and algorithm driver for the
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* MPC107/Tsi107 PowerPC northbridge and processors that include
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* the same I2C unit (8240, 8245, 85xx).
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*
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* Release 0.8
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched/signal.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/fsl_devices.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <asm/mpc52xx.h>
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#include <asm/mpc85xx.h>
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#include <sysdev/fsl_soc.h>
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#define DRV_NAME "mpc-i2c"
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#define MPC_I2C_CLOCK_LEGACY 0
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#define MPC_I2C_CLOCK_PRESERVE (~0U)
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#define MPC_I2C_FDR 0x04
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#define MPC_I2C_CR 0x08
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#define MPC_I2C_SR 0x0c
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#define MPC_I2C_DR 0x10
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#define MPC_I2C_DFSRR 0x14
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#define CCR_MEN 0x80
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#define CCR_MIEN 0x40
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#define CCR_MSTA 0x20
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#define CCR_MTX 0x10
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#define CCR_TXAK 0x08
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#define CCR_RSTA 0x04
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#define CSR_MCF 0x80
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#define CSR_MAAS 0x40
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#define CSR_MBB 0x20
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#define CSR_MAL 0x10
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#define CSR_SRW 0x04
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#define CSR_MIF 0x02
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#define CSR_RXAK 0x01
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struct mpc_i2c {
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struct device *dev;
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void __iomem *base;
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u32 interrupt;
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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u32 real_clk;
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#ifdef CONFIG_PM_SLEEP
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u8 fdr, dfsrr;
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#endif
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struct clk *clk_per;
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};
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struct mpc_i2c_divider {
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u16 divider;
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u16 fdr; /* including dfsrr */
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};
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struct mpc_i2c_data {
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void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
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};
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static inline void writeccr(struct mpc_i2c *i2c, u32 x)
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{
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writeb(x, i2c->base + MPC_I2C_CR);
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}
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static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
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{
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struct mpc_i2c *i2c = dev_id;
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if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
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/* Read again to allow register to stabilise */
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i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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wake_up(&i2c->queue);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
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* the bus, because it wants to send ACK.
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* Following sequence of enabling/disabling and sending start/stop generates
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* the 9 pulses, so it's all OK.
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*/
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static void mpc_i2c_fixup(struct mpc_i2c *i2c)
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{
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int k;
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u32 delay_val = 1000000 / i2c->real_clk + 1;
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if (delay_val < 2)
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delay_val = 2;
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for (k = 9; k; k--) {
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writeccr(i2c, 0);
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writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
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readb(i2c->base + MPC_I2C_DR);
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writeccr(i2c, CCR_MEN);
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udelay(delay_val << 1);
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}
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}
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static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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{
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unsigned long orig_jiffies = jiffies;
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u32 cmd_err;
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int result = 0;
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if (!i2c->irq) {
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while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
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schedule();
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if (time_after(jiffies, orig_jiffies + timeout)) {
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dev_dbg(i2c->dev, "timeout\n");
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writeccr(i2c, 0);
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result = -ETIMEDOUT;
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break;
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}
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}
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cmd_err = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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} else {
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/* Interrupt mode */
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result = wait_event_timeout(i2c->queue,
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(i2c->interrupt & CSR_MIF), timeout);
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if (unlikely(!(i2c->interrupt & CSR_MIF))) {
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dev_dbg(i2c->dev, "wait timeout\n");
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writeccr(i2c, 0);
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result = -ETIMEDOUT;
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}
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cmd_err = i2c->interrupt;
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i2c->interrupt = 0;
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}
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if (result < 0)
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return result;
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if (!(cmd_err & CSR_MCF)) {
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dev_dbg(i2c->dev, "unfinished\n");
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return -EIO;
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}
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if (cmd_err & CSR_MAL) {
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dev_dbg(i2c->dev, "MAL\n");
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return -EAGAIN;
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}
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if (writing && (cmd_err & CSR_RXAK)) {
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dev_dbg(i2c->dev, "No RXAK\n");
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/* generate stop */
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writeccr(i2c, CCR_MEN);
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return -ENXIO;
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}
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return 0;
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}
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#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
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static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
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{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
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{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
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{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
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{52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
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{68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
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{96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
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{128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
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{176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
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{240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
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{320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
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{448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
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{640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
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{1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
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{1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
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{2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
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{4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
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{7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
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{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
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};
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static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
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u32 *real_clk)
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{
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const struct mpc_i2c_divider *div = NULL;
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unsigned int pvr = mfspr(SPRN_PVR);
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u32 divider;
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int i;
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if (clock == MPC_I2C_CLOCK_LEGACY) {
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/* see below - default fdr = 0x3f -> div = 2048 */
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*real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
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return -EINVAL;
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}
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/* Determine divider value */
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divider = mpc5xxx_get_bus_frequency(node) / clock;
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed.
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*/
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for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
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div = &mpc_i2c_dividers_52xx[i];
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/* Old MPC5200 rev A CPUs do not support the high bits */
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if (div->fdr & 0xc0 && pvr == 0x80822011)
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continue;
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if (div->divider >= divider)
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break;
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}
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*real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
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return (int)div->fdr;
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}
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static void mpc_i2c_setup_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock)
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{
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int ret, fdr;
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if (clock == MPC_I2C_CLOCK_PRESERVE) {
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dev_dbg(i2c->dev, "using fdr %d\n",
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readb(i2c->base + MPC_I2C_FDR));
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return;
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}
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ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
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fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
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writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
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if (ret >= 0)
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dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
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fdr);
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}
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#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
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static void mpc_i2c_setup_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock)
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{
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}
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#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
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#ifdef CONFIG_PPC_MPC512x
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static void mpc_i2c_setup_512x(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock)
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{
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struct device_node *node_ctrl;
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void __iomem *ctrl;
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const u32 *pval;
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u32 idx;
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/* Enable I2C interrupts for mpc5121 */
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node_ctrl = of_find_compatible_node(NULL, NULL,
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"fsl,mpc5121-i2c-ctrl");
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if (node_ctrl) {
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ctrl = of_iomap(node_ctrl, 0);
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if (ctrl) {
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/* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
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pval = of_get_property(node, "reg", NULL);
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idx = (*pval & 0xff) / 0x20;
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setbits32(ctrl, 1 << (24 + idx * 2));
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iounmap(ctrl);
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}
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of_node_put(node_ctrl);
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}
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/* The clock setup for the 52xx works also fine for the 512x */
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mpc_i2c_setup_52xx(node, i2c, clock);
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}
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#else /* CONFIG_PPC_MPC512x */
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static void mpc_i2c_setup_512x(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock)
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{
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}
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#endif /* CONFIG_PPC_MPC512x */
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#ifdef CONFIG_FSL_SOC
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static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
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{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
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{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
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{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
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{544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
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{672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
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{800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
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{1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
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{1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
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{1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
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{2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
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{3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
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{4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
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{7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
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{12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
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{18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
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{30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
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{49152, 0x011e}, {61440, 0x011f}
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};
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static u32 mpc_i2c_get_sec_cfg_8xxx(void)
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{
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struct device_node *node;
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u32 __iomem *reg;
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u32 val = 0;
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node = of_find_node_by_name(NULL, "global-utilities");
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if (node) {
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const u32 *prop = of_get_property(node, "reg", NULL);
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if (prop) {
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/*
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* Map and check POR Device Status Register 2
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* (PORDEVSR2) at 0xE0014. Note than while MPC8533
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* and MPC8544 indicate SEC frequency ratio
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* configuration as bit 26 in PORDEVSR2, other MPC8xxx
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* parts may store it differently or may not have it
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* at all.
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*/
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reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
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if (!reg)
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printk(KERN_ERR
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"Error: couldn't map PORDEVSR2\n");
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else
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val = in_be32(reg) & 0x00000020; /* sec-cfg */
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iounmap(reg);
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}
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}
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of_node_put(node);
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return val;
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}
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static u32 mpc_i2c_get_prescaler_8xxx(void)
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{
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/*
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* According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
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* may have prescaler 1, 2, or 3, depending on the power-on
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* configuration.
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*/
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u32 prescaler = 1;
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/* mpc85xx */
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if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
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|| pvr_version_is(PVR_VER_E500MC)
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|| pvr_version_is(PVR_VER_E5500)
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|| pvr_version_is(PVR_VER_E6500)) {
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unsigned int svr = mfspr(SPRN_SVR);
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if ((SVR_SOC_VER(svr) == SVR_8540)
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|| (SVR_SOC_VER(svr) == SVR_8541)
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|| (SVR_SOC_VER(svr) == SVR_8560)
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|| (SVR_SOC_VER(svr) == SVR_8555)
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|| (SVR_SOC_VER(svr) == SVR_8610))
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/* the above 85xx SoCs have prescaler 1 */
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prescaler = 1;
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else if ((SVR_SOC_VER(svr) == SVR_8533)
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|| (SVR_SOC_VER(svr) == SVR_8544))
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/* the above 85xx SoCs have prescaler 3 or 2 */
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prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
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else
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/* all the other 85xx have prescaler 2 */
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prescaler = 2;
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}
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return prescaler;
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}
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static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
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u32 *real_clk)
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{
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const struct mpc_i2c_divider *div = NULL;
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u32 prescaler = mpc_i2c_get_prescaler_8xxx();
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u32 divider;
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int i;
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if (clock == MPC_I2C_CLOCK_LEGACY) {
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/* see below - default fdr = 0x1031 -> div = 16 * 3072 */
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*real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
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return -EINVAL;
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}
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divider = fsl_get_sys_freq() / clock / prescaler;
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pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
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fsl_get_sys_freq(), clock, divider);
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed.
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*/
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for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
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div = &mpc_i2c_dividers_8xxx[i];
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if (div->divider >= divider)
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break;
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}
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*real_clk = fsl_get_sys_freq() / prescaler / div->divider;
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return div ? (int)div->fdr : -EINVAL;
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}
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static void mpc_i2c_setup_8xxx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock)
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{
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int ret, fdr;
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if (clock == MPC_I2C_CLOCK_PRESERVE) {
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dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
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readb(i2c->base + MPC_I2C_DFSRR),
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readb(i2c->base + MPC_I2C_FDR));
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return;
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}
|
|
|
|
ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
|
|
fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
|
|
|
|
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
|
|
writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
|
|
|
|
if (ret >= 0)
|
|
dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
|
|
i2c->real_clk, fdr >> 8, fdr & 0xff);
|
|
}
|
|
|
|
#else /* !CONFIG_FSL_SOC */
|
|
static void mpc_i2c_setup_8xxx(struct device_node *node,
|
|
struct mpc_i2c *i2c,
|
|
u32 clock)
|
|
{
|
|
}
|
|
#endif /* CONFIG_FSL_SOC */
|
|
|
|
static void mpc_i2c_start(struct mpc_i2c *i2c)
|
|
{
|
|
/* Clear arbitration */
|
|
writeb(0, i2c->base + MPC_I2C_SR);
|
|
/* Start with MEN */
|
|
writeccr(i2c, CCR_MEN);
|
|
}
|
|
|
|
static void mpc_i2c_stop(struct mpc_i2c *i2c)
|
|
{
|
|
writeccr(i2c, CCR_MEN);
|
|
}
|
|
|
|
static int mpc_write(struct mpc_i2c *i2c, int target,
|
|
const u8 *data, int length, int restart)
|
|
{
|
|
int i, result;
|
|
unsigned timeout = i2c->adap.timeout;
|
|
u32 flags = restart ? CCR_RSTA : 0;
|
|
|
|
/* Start as master */
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
|
|
/* Write target byte */
|
|
writeb((target << 1), i2c->base + MPC_I2C_DR);
|
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
if (result < 0)
|
|
return result;
|
|
|
|
for (i = 0; i < length; i++) {
|
|
/* Write data byte */
|
|
writeb(data[i], i2c->base + MPC_I2C_DR);
|
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
if (result < 0)
|
|
return result;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mpc_read(struct mpc_i2c *i2c, int target,
|
|
u8 *data, int length, int restart, bool recv_len)
|
|
{
|
|
unsigned timeout = i2c->adap.timeout;
|
|
int i, result;
|
|
u32 flags = restart ? CCR_RSTA : 0;
|
|
|
|
/* Switch to read - restart */
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
|
|
/* Write target address byte - this time with the read flag set */
|
|
writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
|
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
if (result < 0)
|
|
return result;
|
|
|
|
if (length) {
|
|
if (length == 1 && !recv_len)
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
|
|
else
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
|
|
/* Dummy read */
|
|
readb(i2c->base + MPC_I2C_DR);
|
|
}
|
|
|
|
for (i = 0; i < length; i++) {
|
|
u8 byte;
|
|
|
|
result = i2c_wait(i2c, timeout, 0);
|
|
if (result < 0)
|
|
return result;
|
|
|
|
/*
|
|
* For block reads, we have to know the total length (1st byte)
|
|
* before we can determine if we are done.
|
|
*/
|
|
if (i || !recv_len) {
|
|
/* Generate txack on next to last byte */
|
|
if (i == length - 2)
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
|
|
| CCR_TXAK);
|
|
/* Do not generate stop on last byte */
|
|
if (i == length - 1)
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
|
|
| CCR_MTX);
|
|
}
|
|
|
|
byte = readb(i2c->base + MPC_I2C_DR);
|
|
|
|
/*
|
|
* Adjust length if first received byte is length.
|
|
* The length is 1 length byte plus actually data length
|
|
*/
|
|
if (i == 0 && recv_len) {
|
|
if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
|
|
return -EPROTO;
|
|
length += byte;
|
|
/*
|
|
* For block reads, generate txack here if data length
|
|
* is 1 byte (total length is 2 bytes).
|
|
*/
|
|
if (length == 2)
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
|
|
| CCR_TXAK);
|
|
}
|
|
data[i] = byte;
|
|
}
|
|
|
|
return length;
|
|
}
|
|
|
|
static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct i2c_msg *pmsg;
|
|
int i;
|
|
int ret = 0;
|
|
unsigned long orig_jiffies = jiffies;
|
|
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
mpc_i2c_start(i2c);
|
|
|
|
/* Allow bus up to 1s to become not busy */
|
|
while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
|
|
if (signal_pending(current)) {
|
|
dev_dbg(i2c->dev, "Interrupted\n");
|
|
writeccr(i2c, 0);
|
|
return -EINTR;
|
|
}
|
|
if (time_after(jiffies, orig_jiffies + HZ)) {
|
|
u8 status = readb(i2c->base + MPC_I2C_SR);
|
|
|
|
dev_dbg(i2c->dev, "timeout\n");
|
|
if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
|
|
writeb(status & ~CSR_MAL,
|
|
i2c->base + MPC_I2C_SR);
|
|
mpc_i2c_fixup(i2c);
|
|
}
|
|
return -EIO;
|
|
}
|
|
schedule();
|
|
}
|
|
|
|
for (i = 0; ret >= 0 && i < num; i++) {
|
|
pmsg = &msgs[i];
|
|
dev_dbg(i2c->dev,
|
|
"Doing %s %d bytes to 0x%02x - %d of %d messages\n",
|
|
pmsg->flags & I2C_M_RD ? "read" : "write",
|
|
pmsg->len, pmsg->addr, i + 1, num);
|
|
if (pmsg->flags & I2C_M_RD) {
|
|
bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
|
|
|
|
ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
|
|
recv_len);
|
|
if (recv_len && ret > 0)
|
|
pmsg->len = ret;
|
|
} else {
|
|
ret =
|
|
mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
|
|
}
|
|
}
|
|
mpc_i2c_stop(i2c); /* Initiate STOP */
|
|
orig_jiffies = jiffies;
|
|
/* Wait until STOP is seen, allow up to 1 s */
|
|
while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
|
|
if (time_after(jiffies, orig_jiffies + HZ)) {
|
|
u8 status = readb(i2c->base + MPC_I2C_SR);
|
|
|
|
dev_dbg(i2c->dev, "timeout\n");
|
|
if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
|
|
writeb(status & ~CSR_MAL,
|
|
i2c->base + MPC_I2C_SR);
|
|
mpc_i2c_fixup(i2c);
|
|
}
|
|
return -EIO;
|
|
}
|
|
cond_resched();
|
|
}
|
|
return (ret < 0) ? ret : num;
|
|
}
|
|
|
|
static u32 mpc_functionality(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
|
|
| I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
|
|
}
|
|
|
|
static const struct i2c_algorithm mpc_algo = {
|
|
.master_xfer = mpc_xfer,
|
|
.functionality = mpc_functionality,
|
|
};
|
|
|
|
static struct i2c_adapter mpc_ops = {
|
|
.owner = THIS_MODULE,
|
|
.algo = &mpc_algo,
|
|
.timeout = HZ,
|
|
};
|
|
|
|
static const struct of_device_id mpc_i2c_of_match[];
|
|
static int fsl_i2c_probe(struct platform_device *op)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct mpc_i2c *i2c;
|
|
const u32 *prop;
|
|
u32 clock = MPC_I2C_CLOCK_LEGACY;
|
|
int result = 0;
|
|
int plen;
|
|
struct resource res;
|
|
struct clk *clk;
|
|
int err;
|
|
|
|
match = of_match_device(mpc_i2c_of_match, &op->dev);
|
|
if (!match)
|
|
return -EINVAL;
|
|
|
|
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
|
|
if (!i2c)
|
|
return -ENOMEM;
|
|
|
|
i2c->dev = &op->dev; /* for debug and error output */
|
|
|
|
init_waitqueue_head(&i2c->queue);
|
|
|
|
i2c->base = of_iomap(op->dev.of_node, 0);
|
|
if (!i2c->base) {
|
|
dev_err(i2c->dev, "failed to map controller\n");
|
|
result = -ENOMEM;
|
|
goto fail_map;
|
|
}
|
|
|
|
i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
|
|
if (i2c->irq) { /* no i2c->irq implies polling */
|
|
result = request_irq(i2c->irq, mpc_i2c_isr,
|
|
IRQF_SHARED, "i2c-mpc", i2c);
|
|
if (result < 0) {
|
|
dev_err(i2c->dev, "failed to attach interrupt\n");
|
|
goto fail_request;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* enable clock for the I2C peripheral (non fatal),
|
|
* keep a reference upon successful allocation
|
|
*/
|
|
clk = devm_clk_get(&op->dev, NULL);
|
|
if (!IS_ERR(clk)) {
|
|
err = clk_prepare_enable(clk);
|
|
if (err) {
|
|
dev_err(&op->dev, "failed to enable clock\n");
|
|
goto fail_request;
|
|
} else {
|
|
i2c->clk_per = clk;
|
|
}
|
|
}
|
|
|
|
if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
|
|
clock = MPC_I2C_CLOCK_PRESERVE;
|
|
} else {
|
|
prop = of_get_property(op->dev.of_node, "clock-frequency",
|
|
&plen);
|
|
if (prop && plen == sizeof(u32))
|
|
clock = *prop;
|
|
}
|
|
|
|
if (match->data) {
|
|
const struct mpc_i2c_data *data = match->data;
|
|
data->setup(op->dev.of_node, i2c, clock);
|
|
} else {
|
|
/* Backwards compatibility */
|
|
if (of_get_property(op->dev.of_node, "dfsrr", NULL))
|
|
mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
|
|
}
|
|
|
|
prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
|
|
if (prop && plen == sizeof(u32)) {
|
|
mpc_ops.timeout = *prop * HZ / 1000000;
|
|
if (mpc_ops.timeout < 5)
|
|
mpc_ops.timeout = 5;
|
|
}
|
|
dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
|
|
|
|
platform_set_drvdata(op, i2c);
|
|
|
|
i2c->adap = mpc_ops;
|
|
of_address_to_resource(op->dev.of_node, 0, &res);
|
|
scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
|
|
"MPC adapter at 0x%llx", (unsigned long long)res.start);
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
i2c->adap.dev.parent = &op->dev;
|
|
i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
|
|
|
|
result = i2c_add_adapter(&i2c->adap);
|
|
if (result < 0)
|
|
goto fail_add;
|
|
|
|
return result;
|
|
|
|
fail_add:
|
|
if (i2c->clk_per)
|
|
clk_disable_unprepare(i2c->clk_per);
|
|
free_irq(i2c->irq, i2c);
|
|
fail_request:
|
|
irq_dispose_mapping(i2c->irq);
|
|
iounmap(i2c->base);
|
|
fail_map:
|
|
kfree(i2c);
|
|
return result;
|
|
};
|
|
|
|
static int fsl_i2c_remove(struct platform_device *op)
|
|
{
|
|
struct mpc_i2c *i2c = platform_get_drvdata(op);
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
if (i2c->clk_per)
|
|
clk_disable_unprepare(i2c->clk_per);
|
|
|
|
if (i2c->irq)
|
|
free_irq(i2c->irq, i2c);
|
|
|
|
irq_dispose_mapping(i2c->irq);
|
|
iounmap(i2c->base);
|
|
kfree(i2c);
|
|
return 0;
|
|
};
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int mpc_i2c_suspend(struct device *dev)
|
|
{
|
|
struct mpc_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
|
|
i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mpc_i2c_resume(struct device *dev)
|
|
{
|
|
struct mpc_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
|
|
writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
|
|
#define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
|
|
#else
|
|
#define MPC_I2C_PM_OPS NULL
|
|
#endif
|
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_512x = {
|
|
.setup = mpc_i2c_setup_512x,
|
|
};
|
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_52xx = {
|
|
.setup = mpc_i2c_setup_52xx,
|
|
};
|
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_8313 = {
|
|
.setup = mpc_i2c_setup_8xxx,
|
|
};
|
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_8543 = {
|
|
.setup = mpc_i2c_setup_8xxx,
|
|
};
|
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_8544 = {
|
|
.setup = mpc_i2c_setup_8xxx,
|
|
};
|
|
|
|
static const struct of_device_id mpc_i2c_of_match[] = {
|
|
{.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
|
|
{.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
|
|
{.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
|
|
{.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
|
|
{.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
|
|
{.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
|
|
{.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
|
|
/* Backward compatibility */
|
|
{.compatible = "fsl-i2c", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
|
|
|
|
/* Structure for a device driver */
|
|
static struct platform_driver mpc_i2c_driver = {
|
|
.probe = fsl_i2c_probe,
|
|
.remove = fsl_i2c_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = mpc_i2c_of_match,
|
|
.pm = MPC_I2C_PM_OPS,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mpc_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
|
|
MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
|
|
"MPC824x/83xx/85xx/86xx/512x/52xx processors");
|
|
MODULE_LICENSE("GPL");
|