750 lines
19 KiB
C
750 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include "i2c-designware-core.h"
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static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
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{
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/* Configure Tx/Rx FIFO threshold levels */
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dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
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dw_writel(dev, 0, DW_IC_RX_TL);
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/* Configure the I2C master */
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dw_writel(dev, dev->master_cfg, DW_IC_CON);
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}
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static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
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{
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const char *mode_str, *fp_str = "";
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u32 comp_param1;
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u32 sda_falling_time, scl_falling_time;
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struct i2c_timings *t = &dev->timings;
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u32 ic_clk;
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
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i2c_dw_release_lock(dev);
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/* Set standard and fast speed dividers for high/low periods */
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sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
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scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
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/* Calculate SCL timing parameters for standard mode if not set */
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if (!dev->ss_hcnt || !dev->ss_lcnt) {
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ic_clk = i2c_dw_clk_rate(dev);
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dev->ss_hcnt =
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i2c_dw_scl_hcnt(ic_clk,
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4000, /* tHD;STA = tHIGH = 4.0 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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dev->ss_lcnt =
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i2c_dw_scl_lcnt(ic_clk,
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4700, /* tLOW = 4.7 us */
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scl_falling_time,
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0); /* No offset */
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}
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dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
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dev->ss_hcnt, dev->ss_lcnt);
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/*
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* Set SCL timing parameters for fast mode or fast mode plus. Only
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* difference is the timing parameter values since the registers are
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* the same.
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*/
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if (t->bus_freq_hz == 1000000) {
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/*
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* Check are fast mode plus parameters available and use
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* fast mode if not.
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*/
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if (dev->fp_hcnt && dev->fp_lcnt) {
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dev->fs_hcnt = dev->fp_hcnt;
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dev->fs_lcnt = dev->fp_lcnt;
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fp_str = " Plus";
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}
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}
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/*
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* Calculate SCL timing parameters for fast mode if not set. They are
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* needed also in high speed mode.
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*/
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if (!dev->fs_hcnt || !dev->fs_lcnt) {
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ic_clk = i2c_dw_clk_rate(dev);
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dev->fs_hcnt =
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i2c_dw_scl_hcnt(ic_clk,
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600, /* tHD;STA = tHIGH = 0.6 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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dev->fs_lcnt =
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i2c_dw_scl_lcnt(ic_clk,
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1300, /* tLOW = 1.3 us */
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scl_falling_time,
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0); /* No offset */
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}
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dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
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fp_str, dev->fs_hcnt, dev->fs_lcnt);
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/* Check is high speed possible and fall back to fast mode if not */
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if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
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DW_IC_CON_SPEED_HIGH) {
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if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
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!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
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dev_err(dev->dev, "High Speed not supported!\n");
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dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
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dev->master_cfg |= DW_IC_CON_SPEED_FAST;
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dev->hs_hcnt = 0;
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dev->hs_lcnt = 0;
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} else if (dev->hs_hcnt && dev->hs_lcnt) {
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dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
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dev->hs_hcnt, dev->hs_lcnt);
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}
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}
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ret = i2c_dw_set_sda_hold(dev);
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if (ret)
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goto out;
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switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
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case DW_IC_CON_SPEED_STD:
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mode_str = "Standard Mode";
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break;
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case DW_IC_CON_SPEED_HIGH:
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mode_str = "High Speed Mode";
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break;
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default:
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mode_str = "Fast Mode";
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}
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dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
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out:
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return ret;
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}
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/**
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* i2c_dw_init() - Initialize the designware I2C master hardware
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* @dev: device private data
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*
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* This functions configures and enables the I2C master.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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static int i2c_dw_init_master(struct dw_i2c_dev *dev)
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{
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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/* Disable the adapter */
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__i2c_dw_disable(dev);
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/* Write standard speed timing parameters */
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dw_writel(dev, dev->ss_hcnt, DW_IC_SS_SCL_HCNT);
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dw_writel(dev, dev->ss_lcnt, DW_IC_SS_SCL_LCNT);
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/* Write fast mode/fast mode plus timing parameters */
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dw_writel(dev, dev->fs_hcnt, DW_IC_FS_SCL_HCNT);
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dw_writel(dev, dev->fs_lcnt, DW_IC_FS_SCL_LCNT);
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/* Write high speed timing parameters if supported */
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if (dev->hs_hcnt && dev->hs_lcnt) {
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dw_writel(dev, dev->hs_hcnt, DW_IC_HS_SCL_HCNT);
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dw_writel(dev, dev->hs_lcnt, DW_IC_HS_SCL_LCNT);
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}
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/* Write SDA hold time if supported */
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if (dev->sda_hold_time)
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dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
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i2c_dw_configure_fifo_master(dev);
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i2c_dw_release_lock(dev);
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return 0;
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}
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 ic_con, ic_tar = 0;
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/* Disable the adapter */
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__i2c_dw_disable(dev);
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/* If the slave address is ten bit address, enable 10BITADDR */
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ic_con = dw_readl(dev, DW_IC_CON);
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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/*
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* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
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* mode has to be enabled via bit 12 of IC_TAR register.
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* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
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* detected from registers.
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*/
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ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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} else {
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ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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}
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dw_writel(dev, ic_con, DW_IC_CON);
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/*
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* Set the slave (target) address and enable 10-bit addressing mode
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* if applicable.
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*/
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dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
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/* Enforce disabled interrupts (due to HW issues) */
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i2c_dw_disable_int(dev);
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/* Enable the adapter */
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__i2c_dw_enable(dev);
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/* Dummy read to avoid the register getting stuck on Bay Trail */
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dw_readl(dev, DW_IC_ENABLE_STATUS);
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/* Clear and enable interrupts */
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dw_readl(dev, DW_IC_CLR_INTR);
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dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
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}
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/*
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* Initiate (and continue) low level master read/write transaction.
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* This function is only called from i2c_dw_isr, and pumping i2c_msg
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* messages into the tx buffer. Even if the size of i2c_msg data is
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* longer than the size of the tx buffer, it handles everything.
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*/
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static void
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i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 intr_mask;
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int tx_limit, rx_limit;
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u32 addr = msgs[dev->msg_write_idx].addr;
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u32 buf_len = dev->tx_buf_len;
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u8 *buf = dev->tx_buf;
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bool need_restart = false;
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intr_mask = DW_IC_INTR_MASTER_MASK;
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for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
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u32 flags = msgs[dev->msg_write_idx].flags;
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/*
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* If target address has changed, we need to
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* reprogram the target address in the I2C
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* adapter when we are done with this transfer.
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*/
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if (msgs[dev->msg_write_idx].addr != addr) {
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dev_err(dev->dev,
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"%s: invalid target address\n", __func__);
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dev->msg_err = -EINVAL;
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break;
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}
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if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
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/* new i2c_msg */
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buf = msgs[dev->msg_write_idx].buf;
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buf_len = msgs[dev->msg_write_idx].len;
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/* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
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* IC_RESTART_EN are set, we must manually
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* set restart bit between messages.
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*/
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if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
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(dev->msg_write_idx > 0))
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need_restart = true;
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}
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tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
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rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
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while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
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u32 cmd = 0;
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/*
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* If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
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* manually set the stop bit. However, it cannot be
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* detected from the registers so we set it always
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* when writing/reading the last byte.
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*/
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/*
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* i2c-core always sets the buffer length of
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* I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
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* be adjusted when receiving the first byte.
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* Thus we can't stop the transaction here.
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*/
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if (dev->msg_write_idx == dev->msgs_num - 1 &&
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buf_len == 1 && !(flags & I2C_M_RECV_LEN))
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cmd |= BIT(9);
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if (need_restart) {
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cmd |= BIT(10);
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need_restart = false;
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}
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if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
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/* Avoid rx buffer overrun */
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if (dev->rx_outstanding >= dev->rx_fifo_depth)
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break;
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dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
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rx_limit--;
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dev->rx_outstanding++;
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} else
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dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
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tx_limit--; buf_len--;
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}
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dev->tx_buf = buf;
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dev->tx_buf_len = buf_len;
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/*
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* Because we don't know the buffer length in the
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* I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
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* the transaction here.
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*/
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if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
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/* more bytes to be written */
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dev->status |= STATUS_WRITE_IN_PROGRESS;
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break;
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} else
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dev->status &= ~STATUS_WRITE_IN_PROGRESS;
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}
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/*
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* If i2c_msg index search is completed, we don't need TX_EMPTY
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* interrupt any more.
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*/
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if (dev->msg_write_idx == dev->msgs_num)
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intr_mask &= ~DW_IC_INTR_TX_EMPTY;
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if (dev->msg_err)
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intr_mask = 0;
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dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
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}
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static u8
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i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 flags = msgs[dev->msg_read_idx].flags;
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/*
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* Adjust the buffer length and mask the flag
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* after receiving the first byte.
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*/
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len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
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dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
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msgs[dev->msg_read_idx].len = len;
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msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
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return len;
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}
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static void
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i2c_dw_read(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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int rx_valid;
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for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
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u32 len;
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u8 *buf;
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if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
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continue;
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if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
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len = msgs[dev->msg_read_idx].len;
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buf = msgs[dev->msg_read_idx].buf;
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} else {
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len = dev->rx_buf_len;
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buf = dev->rx_buf;
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}
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rx_valid = dw_readl(dev, DW_IC_RXFLR);
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for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
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u32 flags = msgs[dev->msg_read_idx].flags;
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*buf = dw_readl(dev, DW_IC_DATA_CMD);
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/* Ensure length byte is a valid value */
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if (flags & I2C_M_RECV_LEN &&
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*buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
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len = i2c_dw_recv_len(dev, *buf);
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}
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buf++;
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dev->rx_outstanding--;
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}
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if (len > 0) {
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dev->status |= STATUS_READ_IN_PROGRESS;
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dev->rx_buf_len = len;
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dev->rx_buf = buf;
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return;
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} else
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dev->status &= ~STATUS_READ_IN_PROGRESS;
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}
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}
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/*
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* Prepare controller for a transaction and call i2c_dw_xfer_msg.
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*/
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static int
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i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int ret;
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dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
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pm_runtime_get_sync(dev->dev);
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if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
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ret = -ESHUTDOWN;
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goto done_nolock;
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}
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reinit_completion(&dev->cmd_complete);
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dev->msgs = msgs;
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dev->msgs_num = num;
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dev->cmd_err = 0;
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dev->msg_write_idx = 0;
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dev->msg_read_idx = 0;
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dev->msg_err = 0;
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dev->status = STATUS_IDLE;
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dev->abort_source = 0;
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dev->rx_outstanding = 0;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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goto done_nolock;
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ret = i2c_dw_wait_bus_not_busy(dev);
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if (ret < 0)
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goto done;
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/* Start the transfers */
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i2c_dw_xfer_init(dev);
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/* Wait for tx to complete */
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if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
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dev_err(dev->dev, "controller timed out\n");
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/* i2c_dw_init implicitly disables the adapter */
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i2c_recover_bus(&dev->adapter);
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i2c_dw_init_master(dev);
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ret = -ETIMEDOUT;
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goto done;
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}
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/*
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* We must disable the adapter before returning and signaling the end
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* of the current transfer. Otherwise the hardware might continue
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* generating interrupts which in turn causes a race condition with
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* the following transfer. Needs some more investigation if the
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* additional interrupts are a hardware bug or this driver doesn't
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* handle them correctly yet.
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*/
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__i2c_dw_disable_nowait(dev);
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if (dev->msg_err) {
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ret = dev->msg_err;
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goto done;
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}
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/* No error */
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if (likely(!dev->cmd_err && !dev->status)) {
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ret = num;
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goto done;
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}
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/* We have an error */
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if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
|
|
ret = i2c_dw_handle_tx_abort(dev);
|
|
goto done;
|
|
}
|
|
|
|
if (dev->status)
|
|
dev_err(dev->dev,
|
|
"transfer terminated early - interrupt latency too high?\n");
|
|
|
|
ret = -EIO;
|
|
|
|
done:
|
|
i2c_dw_release_lock(dev);
|
|
|
|
done_nolock:
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct i2c_algorithm i2c_dw_algo = {
|
|
.master_xfer = i2c_dw_xfer,
|
|
.functionality = i2c_dw_func,
|
|
};
|
|
|
|
static const struct i2c_adapter_quirks i2c_dw_quirks = {
|
|
.flags = I2C_AQ_NO_ZERO_LEN,
|
|
};
|
|
|
|
static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
|
|
{
|
|
u32 stat;
|
|
|
|
/*
|
|
* The IC_INTR_STAT register just indicates "enabled" interrupts.
|
|
* Ths unmasked raw version of interrupt status bits are available
|
|
* in the IC_RAW_INTR_STAT register.
|
|
*
|
|
* That is,
|
|
* stat = dw_readl(IC_INTR_STAT);
|
|
* equals to,
|
|
* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
|
|
*
|
|
* The raw version might be useful for debugging purposes.
|
|
*/
|
|
stat = dw_readl(dev, DW_IC_INTR_STAT);
|
|
|
|
/*
|
|
* Do not use the IC_CLR_INTR register to clear interrupts, or
|
|
* you'll miss some interrupts, triggered during the period from
|
|
* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
|
|
*
|
|
* Instead, use the separately-prepared IC_CLR_* registers.
|
|
*/
|
|
if (stat & DW_IC_INTR_RX_UNDER)
|
|
dw_readl(dev, DW_IC_CLR_RX_UNDER);
|
|
if (stat & DW_IC_INTR_RX_OVER)
|
|
dw_readl(dev, DW_IC_CLR_RX_OVER);
|
|
if (stat & DW_IC_INTR_TX_OVER)
|
|
dw_readl(dev, DW_IC_CLR_TX_OVER);
|
|
if (stat & DW_IC_INTR_RD_REQ)
|
|
dw_readl(dev, DW_IC_CLR_RD_REQ);
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
/*
|
|
* The IC_TX_ABRT_SOURCE register is cleared whenever
|
|
* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
|
|
*/
|
|
dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
|
|
dw_readl(dev, DW_IC_CLR_TX_ABRT);
|
|
}
|
|
if (stat & DW_IC_INTR_RX_DONE)
|
|
dw_readl(dev, DW_IC_CLR_RX_DONE);
|
|
if (stat & DW_IC_INTR_ACTIVITY)
|
|
dw_readl(dev, DW_IC_CLR_ACTIVITY);
|
|
if (stat & DW_IC_INTR_STOP_DET)
|
|
dw_readl(dev, DW_IC_CLR_STOP_DET);
|
|
if (stat & DW_IC_INTR_START_DET)
|
|
dw_readl(dev, DW_IC_CLR_START_DET);
|
|
if (stat & DW_IC_INTR_GEN_CALL)
|
|
dw_readl(dev, DW_IC_CLR_GEN_CALL);
|
|
|
|
return stat;
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine. This gets called whenever an I2C master interrupt
|
|
* occurs.
|
|
*/
|
|
static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
|
|
{
|
|
u32 stat;
|
|
|
|
stat = i2c_dw_read_clear_intrbits(dev);
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
dev->cmd_err |= DW_IC_ERR_TX_ABRT;
|
|
dev->status = STATUS_IDLE;
|
|
|
|
/*
|
|
* Anytime TX_ABRT is set, the contents of the tx/rx
|
|
* buffers are flushed. Make sure to skip them.
|
|
*/
|
|
dw_writel(dev, 0, DW_IC_INTR_MASK);
|
|
goto tx_aborted;
|
|
}
|
|
|
|
if (stat & DW_IC_INTR_RX_FULL)
|
|
i2c_dw_read(dev);
|
|
|
|
if (stat & DW_IC_INTR_TX_EMPTY)
|
|
i2c_dw_xfer_msg(dev);
|
|
|
|
/*
|
|
* No need to modify or disable the interrupt mask here.
|
|
* i2c_dw_xfer_msg() will take care of it according to
|
|
* the current transmit status.
|
|
*/
|
|
|
|
tx_aborted:
|
|
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
|
|
complete(&dev->cmd_complete);
|
|
else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
|
|
/* Workaround to trigger pending interrupt */
|
|
stat = dw_readl(dev, DW_IC_INTR_MASK);
|
|
i2c_dw_disable_int(dev);
|
|
dw_writel(dev, stat, DW_IC_INTR_MASK);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
|
{
|
|
struct dw_i2c_dev *dev = dev_id;
|
|
u32 stat, enabled;
|
|
|
|
enabled = dw_readl(dev, DW_IC_ENABLE);
|
|
stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
|
|
dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
|
|
if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
|
|
return IRQ_NONE;
|
|
|
|
i2c_dw_irq_handler_master(dev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
i2c_dw_disable(dev);
|
|
reset_control_assert(dev->rst);
|
|
i2c_dw_prepare_clk(dev, false);
|
|
}
|
|
|
|
static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
i2c_dw_prepare_clk(dev, true);
|
|
reset_control_deassert(dev->rst);
|
|
i2c_dw_init_master(dev);
|
|
}
|
|
|
|
static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
|
|
struct i2c_adapter *adap = &dev->adapter;
|
|
struct gpio_desc *gpio;
|
|
|
|
gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
|
|
if (IS_ERR_OR_NULL(gpio))
|
|
return PTR_ERR_OR_ZERO(gpio);
|
|
|
|
rinfo->scl_gpiod = gpio;
|
|
|
|
gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
|
|
if (IS_ERR(gpio))
|
|
return PTR_ERR(gpio);
|
|
rinfo->sda_gpiod = gpio;
|
|
|
|
rinfo->recover_bus = i2c_generic_scl_recovery;
|
|
rinfo->prepare_recovery = i2c_dw_prepare_recovery;
|
|
rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
|
|
adap->bus_recovery_info = rinfo;
|
|
|
|
dev_info(dev->dev, "running with gpio recovery mode! scl%s",
|
|
rinfo->sda_gpiod ? ",sda" : "");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i2c_dw_probe(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_adapter *adap = &dev->adapter;
|
|
unsigned long irq_flags;
|
|
int ret;
|
|
|
|
init_completion(&dev->cmd_complete);
|
|
|
|
dev->init = i2c_dw_init_master;
|
|
dev->disable = i2c_dw_disable;
|
|
dev->disable_int = i2c_dw_disable_int;
|
|
|
|
ret = i2c_dw_set_reg_access(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = i2c_dw_set_timings_master(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = dev->init(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
snprintf(adap->name, sizeof(adap->name),
|
|
"Synopsys DesignWare I2C adapter");
|
|
adap->retries = 3;
|
|
adap->algo = &i2c_dw_algo;
|
|
adap->quirks = &i2c_dw_quirks;
|
|
adap->dev.parent = dev->dev;
|
|
i2c_set_adapdata(adap, dev);
|
|
|
|
if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
|
|
irq_flags = IRQF_NO_SUSPEND;
|
|
} else {
|
|
irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
|
|
}
|
|
|
|
i2c_dw_disable_int(dev);
|
|
ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
|
|
dev_name(dev->dev), dev);
|
|
if (ret) {
|
|
dev_err(dev->dev, "failure requesting irq %i: %d\n",
|
|
dev->irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = i2c_dw_init_recovery_info(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Increment PM usage count during adapter registration in order to
|
|
* avoid possible spurious runtime suspend when adapter device is
|
|
* registered to the device core and immediate resume in case bus has
|
|
* registered I2C slaves that do I2C transfers in their probe.
|
|
*/
|
|
pm_runtime_get_noresume(dev->dev);
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
if (ret)
|
|
dev_err(dev->dev, "failure adding adapter: %d\n", ret);
|
|
pm_runtime_put_noidle(dev->dev);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_probe);
|
|
|
|
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
|
|
MODULE_LICENSE("GPL");
|