157 lines
5.6 KiB
C
157 lines
5.6 KiB
C
/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ICP_QAT_HAL_H
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#define __ICP_QAT_HAL_H
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#include "icp_qat_fw_loader_handle.h"
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enum hal_global_csr {
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MISC_CONTROL = 0x04,
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ICP_RESET = 0x0c,
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ICP_GLOBAL_CLK_ENABLE = 0x50
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};
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enum hal_ae_csr {
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USTORE_ADDRESS = 0x000,
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USTORE_DATA_LOWER = 0x004,
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USTORE_DATA_UPPER = 0x008,
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ALU_OUT = 0x010,
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CTX_ARB_CNTL = 0x014,
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CTX_ENABLES = 0x018,
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CC_ENABLE = 0x01c,
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CSR_CTX_POINTER = 0x020,
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CTX_STS_INDIRECT = 0x040,
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ACTIVE_CTX_STATUS = 0x044,
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CTX_SIG_EVENTS_INDIRECT = 0x048,
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CTX_SIG_EVENTS_ACTIVE = 0x04c,
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CTX_WAKEUP_EVENTS_INDIRECT = 0x050,
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LM_ADDR_0_INDIRECT = 0x060,
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LM_ADDR_1_INDIRECT = 0x068,
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INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0,
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INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8,
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FUTURE_COUNT_SIGNAL_INDIRECT = 0x078,
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TIMESTAMP_LOW = 0x0c0,
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TIMESTAMP_HIGH = 0x0c4,
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PROFILE_COUNT = 0x144,
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SIGNATURE_ENABLE = 0x150,
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AE_MISC_CONTROL = 0x160,
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LOCAL_CSR_STATUS = 0x180,
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};
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enum fcu_csr {
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FCU_CONTROL = 0x8c0,
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FCU_STATUS = 0x8c4,
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FCU_STATUS1 = 0x8c8,
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FCU_DRAM_ADDR_LO = 0x8cc,
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FCU_DRAM_ADDR_HI = 0x8d0,
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FCU_RAMBASE_ADDR_HI = 0x8d4,
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FCU_RAMBASE_ADDR_LO = 0x8d8
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};
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enum fcu_cmd {
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FCU_CTRL_CMD_NOOP = 0,
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FCU_CTRL_CMD_AUTH = 1,
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FCU_CTRL_CMD_LOAD = 2,
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FCU_CTRL_CMD_START = 3
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};
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enum fcu_sts {
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FCU_STS_NO_STS = 0,
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FCU_STS_VERI_DONE = 1,
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FCU_STS_LOAD_DONE = 2,
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FCU_STS_VERI_FAIL = 3,
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FCU_STS_LOAD_FAIL = 4,
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FCU_STS_BUSY = 5
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};
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#define UA_ECS (0x1 << 31)
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#define ACS_ABO_BITPOS 31
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#define ACS_ACNO 0x7
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#define CE_ENABLE_BITPOS 0x8
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#define CE_LMADDR_0_GLOBAL_BITPOS 16
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#define CE_LMADDR_1_GLOBAL_BITPOS 17
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#define CE_NN_MODE_BITPOS 20
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#define CE_REG_PAR_ERR_BITPOS 25
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#define CE_BREAKPOINT_BITPOS 27
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#define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29
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#define CE_INUSE_CONTEXTS_BITPOS 31
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#define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS)
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#define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS)
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#define XCWE_VOLUNTARY (0x1)
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#define LCS_STATUS (0x1)
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#define MMC_SHARE_CS_BITPOS 2
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#define GLOBAL_CSR 0xA00
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#define FCU_CTRL_AE_POS 0x8
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#define FCU_AUTH_STS_MASK 0x7
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#define FCU_STS_DONE_POS 0x9
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#define FCU_STS_AUTHFWLD_POS 0X8
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#define FCU_LOADED_AE_POS 0x16
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#define FW_AUTH_WAIT_PERIOD 10
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#define FW_AUTH_MAX_RETRY 300
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#define SET_CAP_CSR(handle, csr, val) \
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ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
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#define GET_CAP_CSR(handle, csr) \
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ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
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#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
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#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
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#define AE_CSR(handle, ae) \
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((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \
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((ae & handle->hal_handle->ae_mask) << 12))
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#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
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#define SET_AE_CSR(handle, ae, csr, val) \
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ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
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#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
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#define AE_XFER(handle, ae) \
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((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \
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((ae & handle->hal_handle->ae_mask) << 12))
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#define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
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((reg & 0xff) << 2))
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#define SET_AE_XFER(handle, ae, reg, val) \
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ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
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#define SRAM_WRITE(handle, addr, val) \
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ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
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#endif
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