139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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/*
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* The AO Domain embeds a dual/divider to generate a more precise
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* 32,768KHz clock for low-power suspend mode and CEC.
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* ______ ______
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* | | | |
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* | Div1 |-| Cnt1 |
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* /|______| |______|\
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* -| ______ ______ X--> Out
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* \| | | |/
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* | Div2 |-| Cnt2 |
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* |______| |______|
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*
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* The dividing can be switched to single or dual, with a counter
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* for each divider to set when the switching is done.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include "clk-regmap.h"
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#include "clk-dualdiv.h"
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static inline struct meson_clk_dualdiv_data *
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meson_clk_dualdiv_data(struct clk_regmap *clk)
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{
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return (struct meson_clk_dualdiv_data *)clk->data;
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}
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static unsigned long
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__dualdiv_param_to_rate(unsigned long parent_rate,
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const struct meson_clk_dualdiv_param *p)
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{
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if (!p->dual)
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return DIV_ROUND_CLOSEST(parent_rate, p->n1);
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return DIV_ROUND_CLOSEST(parent_rate * (p->m1 + p->m2),
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p->n1 * p->m1 + p->n2 * p->m2);
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}
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static unsigned long meson_clk_dualdiv_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk);
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struct meson_clk_dualdiv_param setting;
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setting.dual = meson_parm_read(clk->map, &dualdiv->dual);
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setting.n1 = meson_parm_read(clk->map, &dualdiv->n1) + 1;
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setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1;
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setting.n2 = meson_parm_read(clk->map, &dualdiv->n2) + 1;
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setting.m2 = meson_parm_read(clk->map, &dualdiv->m2) + 1;
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return __dualdiv_param_to_rate(parent_rate, &setting);
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}
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static const struct meson_clk_dualdiv_param *
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__dualdiv_get_setting(unsigned long rate, unsigned long parent_rate,
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struct meson_clk_dualdiv_data *dualdiv)
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{
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const struct meson_clk_dualdiv_param *table = dualdiv->table;
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unsigned long best = 0, now = 0;
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unsigned int i, best_i = 0;
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if (!table)
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return NULL;
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for (i = 0; table[i].n1; i++) {
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now = __dualdiv_param_to_rate(parent_rate, &table[i]);
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/* If we get an exact match, don't bother any further */
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if (now == rate) {
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return &table[i];
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} else if (abs(now - rate) < abs(best - rate)) {
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best = now;
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best_i = i;
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}
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}
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return (struct meson_clk_dualdiv_param *)&table[best_i];
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}
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static long meson_clk_dualdiv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk);
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const struct meson_clk_dualdiv_param *setting =
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__dualdiv_get_setting(rate, *parent_rate, dualdiv);
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if (!setting)
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return meson_clk_dualdiv_recalc_rate(hw, *parent_rate);
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return __dualdiv_param_to_rate(*parent_rate, setting);
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}
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static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk);
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const struct meson_clk_dualdiv_param *setting =
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__dualdiv_get_setting(rate, parent_rate, dualdiv);
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if (!setting)
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return -EINVAL;
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meson_parm_write(clk->map, &dualdiv->dual, setting->dual);
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meson_parm_write(clk->map, &dualdiv->n1, setting->n1 - 1);
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meson_parm_write(clk->map, &dualdiv->m1, setting->m1 - 1);
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meson_parm_write(clk->map, &dualdiv->n2, setting->n2 - 1);
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meson_parm_write(clk->map, &dualdiv->m2, setting->m2 - 1);
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return 0;
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}
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const struct clk_ops meson_clk_dualdiv_ops = {
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.recalc_rate = meson_clk_dualdiv_recalc_rate,
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.round_rate = meson_clk_dualdiv_round_rate,
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.set_rate = meson_clk_dualdiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ops);
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const struct clk_ops meson_clk_dualdiv_ro_ops = {
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.recalc_rate = meson_clk_dualdiv_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ro_ops);
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MODULE_DESCRIPTION("Amlogic dual divider driver");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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