350 lines
8.2 KiB
C
350 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* OPAL IMC interface detection driver
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* Supported on POWERNV platform
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*
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* Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
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* (C) 2017 Anju T Sudhakar, IBM Corporation.
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* (C) 2017 Hemant K Shaw, IBM Corporation.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/crash_dump.h>
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#include <asm/opal.h>
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#include <asm/io.h>
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#include <asm/imc-pmu.h>
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#include <asm/cputhreads.h>
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#include <asm/debugfs.h>
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static struct dentry *imc_debugfs_parent;
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/* Helpers to export imc command and mode via debugfs */
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static int imc_mem_get(void *data, u64 *val)
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{
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*val = cpu_to_be64(*(u64 *)data);
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return 0;
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}
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static int imc_mem_set(void *data, u64 val)
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{
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*(u64 *)data = cpu_to_be64(val);
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_imc_x64, imc_mem_get, imc_mem_set, "0x%016llx\n");
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static struct dentry *imc_debugfs_create_x64(const char *name, umode_t mode,
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struct dentry *parent, u64 *value)
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{
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return debugfs_create_file_unsafe(name, mode, parent,
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value, &fops_imc_x64);
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}
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/*
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* export_imc_mode_and_cmd: Create a debugfs interface
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* for imc_cmd and imc_mode
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* for each node in the system.
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* imc_mode and imc_cmd can be changed by echo into
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* this interface.
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*/
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static void export_imc_mode_and_cmd(struct device_node *node,
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struct imc_pmu *pmu_ptr)
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{
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static u64 loc, *imc_mode_addr, *imc_cmd_addr;
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char mode[16], cmd[16];
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u32 cb_offset;
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struct imc_mem_info *ptr = pmu_ptr->mem_info;
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imc_debugfs_parent = debugfs_create_dir("imc", powerpc_debugfs_root);
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/*
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* Return here, either because 'imc' directory already exists,
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* Or failed to create a new one.
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*/
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if (!imc_debugfs_parent)
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return;
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if (of_property_read_u32(node, "cb_offset", &cb_offset))
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cb_offset = IMC_CNTL_BLK_OFFSET;
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while (ptr->vbase != NULL) {
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loc = (u64)(ptr->vbase) + cb_offset;
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imc_mode_addr = (u64 *)(loc + IMC_CNTL_BLK_MODE_OFFSET);
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sprintf(mode, "imc_mode_%d", (u32)(ptr->id));
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if (!imc_debugfs_create_x64(mode, 0600, imc_debugfs_parent,
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imc_mode_addr))
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goto err;
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imc_cmd_addr = (u64 *)(loc + IMC_CNTL_BLK_CMD_OFFSET);
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sprintf(cmd, "imc_cmd_%d", (u32)(ptr->id));
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if (!imc_debugfs_create_x64(cmd, 0600, imc_debugfs_parent,
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imc_cmd_addr))
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goto err;
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ptr++;
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}
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return;
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err:
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debugfs_remove_recursive(imc_debugfs_parent);
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}
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/*
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* imc_get_mem_addr_nest: Function to get nest counter memory region
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* for each chip
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*/
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static int imc_get_mem_addr_nest(struct device_node *node,
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struct imc_pmu *pmu_ptr,
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u32 offset)
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{
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int nr_chips = 0, i;
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u64 *base_addr_arr, baddr;
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u32 *chipid_arr;
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nr_chips = of_property_count_u32_elems(node, "chip-id");
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if (nr_chips <= 0)
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return -ENODEV;
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base_addr_arr = kcalloc(nr_chips, sizeof(*base_addr_arr), GFP_KERNEL);
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if (!base_addr_arr)
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return -ENOMEM;
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chipid_arr = kcalloc(nr_chips, sizeof(*chipid_arr), GFP_KERNEL);
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if (!chipid_arr) {
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kfree(base_addr_arr);
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return -ENOMEM;
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}
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if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips))
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goto error;
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if (of_property_read_u64_array(node, "base-addr", base_addr_arr,
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nr_chips))
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goto error;
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pmu_ptr->mem_info = kcalloc(nr_chips + 1, sizeof(*pmu_ptr->mem_info),
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GFP_KERNEL);
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if (!pmu_ptr->mem_info)
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goto error;
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for (i = 0; i < nr_chips; i++) {
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pmu_ptr->mem_info[i].id = chipid_arr[i];
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baddr = base_addr_arr[i] + offset;
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pmu_ptr->mem_info[i].vbase = phys_to_virt(baddr);
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}
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pmu_ptr->imc_counter_mmaped = true;
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export_imc_mode_and_cmd(node, pmu_ptr);
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kfree(base_addr_arr);
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kfree(chipid_arr);
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return 0;
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error:
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kfree(base_addr_arr);
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kfree(chipid_arr);
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return -1;
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}
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/*
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* imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index
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* and domain as the inputs.
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* Allocates memory for the struct imc_pmu, sets up its domain, size and offsets
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*/
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static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain)
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{
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int ret = 0;
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struct imc_pmu *pmu_ptr;
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u32 offset;
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/* Return for unknown domain */
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if (domain < 0)
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return -EINVAL;
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/* memory for pmu */
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pmu_ptr = kzalloc(sizeof(*pmu_ptr), GFP_KERNEL);
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if (!pmu_ptr)
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return -ENOMEM;
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/* Set the domain */
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pmu_ptr->domain = domain;
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ret = of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size);
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if (ret) {
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ret = -EINVAL;
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goto free_pmu;
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}
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if (!of_property_read_u32(parent, "offset", &offset)) {
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if (imc_get_mem_addr_nest(parent, pmu_ptr, offset)) {
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ret = -EINVAL;
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goto free_pmu;
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}
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}
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/* Function to register IMC pmu */
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ret = init_imc_pmu(parent, pmu_ptr, pmu_index);
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if (ret) {
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pr_err("IMC PMU %s Register failed\n", pmu_ptr->pmu.name);
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kfree(pmu_ptr->pmu.name);
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if (pmu_ptr->domain == IMC_DOMAIN_NEST)
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kfree(pmu_ptr->mem_info);
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kfree(pmu_ptr);
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return ret;
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}
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return 0;
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free_pmu:
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kfree(pmu_ptr);
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return ret;
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}
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static void disable_nest_pmu_counters(void)
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{
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int nid, cpu;
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const struct cpumask *l_cpumask;
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get_online_cpus();
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for_each_node_with_cpus(nid) {
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l_cpumask = cpumask_of_node(nid);
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cpu = cpumask_first_and(l_cpumask, cpu_online_mask);
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if (cpu >= nr_cpu_ids)
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continue;
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opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
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get_hard_smp_processor_id(cpu));
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}
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put_online_cpus();
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}
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static void disable_core_pmu_counters(void)
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{
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cpumask_t cores_map;
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int cpu, rc;
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get_online_cpus();
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/* Disable the IMC Core functions */
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cores_map = cpu_online_cores_map();
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for_each_cpu(cpu, &cores_map) {
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rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
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get_hard_smp_processor_id(cpu));
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if (rc)
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pr_err("%s: Failed to stop Core (cpu = %d)\n",
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__FUNCTION__, cpu);
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}
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put_online_cpus();
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}
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int get_max_nest_dev(void)
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{
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struct device_node *node;
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u32 pmu_units = 0, type;
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for_each_compatible_node(node, NULL, IMC_DTB_UNIT_COMPAT) {
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if (of_property_read_u32(node, "type", &type))
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continue;
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if (type == IMC_TYPE_CHIP)
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pmu_units++;
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}
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return pmu_units;
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}
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static int opal_imc_counters_probe(struct platform_device *pdev)
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{
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struct device_node *imc_dev = pdev->dev.of_node;
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int pmu_count = 0, domain;
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bool core_imc_reg = false, thread_imc_reg = false;
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u32 type;
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/*
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* Check whether this is kdump kernel. If yes, force the engines to
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* stop and return.
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*/
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if (is_kdump_kernel()) {
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disable_nest_pmu_counters();
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disable_core_pmu_counters();
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return -ENODEV;
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}
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for_each_compatible_node(imc_dev, NULL, IMC_DTB_UNIT_COMPAT) {
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if (of_property_read_u32(imc_dev, "type", &type)) {
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pr_warn("IMC Device without type property\n");
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continue;
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}
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switch (type) {
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case IMC_TYPE_CHIP:
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domain = IMC_DOMAIN_NEST;
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break;
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case IMC_TYPE_CORE:
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domain =IMC_DOMAIN_CORE;
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break;
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case IMC_TYPE_THREAD:
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domain = IMC_DOMAIN_THREAD;
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break;
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case IMC_TYPE_TRACE:
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/*
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* FIXME. Using trace_imc events to monitor application
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* or KVM thread performance can cause a checkstop
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* (system crash).
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* Disable it for now.
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*/
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pr_info_once("IMC: disabling trace_imc PMU\n");
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domain = -1;
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break;
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default:
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pr_warn("IMC Unknown Device type \n");
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domain = -1;
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break;
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}
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if (!imc_pmu_create(imc_dev, pmu_count, domain)) {
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if (domain == IMC_DOMAIN_NEST)
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pmu_count++;
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if (domain == IMC_DOMAIN_CORE)
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core_imc_reg = true;
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if (domain == IMC_DOMAIN_THREAD)
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thread_imc_reg = true;
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}
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}
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/* If none of the nest units are registered, remove debugfs interface */
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if (pmu_count == 0)
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debugfs_remove_recursive(imc_debugfs_parent);
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/* If core imc is not registered, unregister thread-imc */
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if (!core_imc_reg && thread_imc_reg)
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unregister_thread_imc();
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return 0;
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}
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static void opal_imc_counters_shutdown(struct platform_device *pdev)
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{
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/*
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* Function only stops the engines which is bare minimum.
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* TODO: Need to handle proper memory cleanup and pmu
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* unregister.
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*/
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disable_nest_pmu_counters();
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disable_core_pmu_counters();
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}
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static const struct of_device_id opal_imc_match[] = {
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{ .compatible = IMC_DTB_COMPAT },
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{},
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};
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static struct platform_driver opal_imc_driver = {
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.driver = {
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.name = "opal-imc-counters",
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.of_match_table = opal_imc_match,
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},
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.probe = opal_imc_counters_probe,
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.shutdown = opal_imc_counters_shutdown,
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};
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builtin_platform_driver(opal_imc_driver);
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