188 lines
4.2 KiB
C
188 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Atomic operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/types.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define ATOMIC_INIT(i) { (i) }
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/* Normal writes in our arch don't clear lock reservations */
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static inline void atomic_set(atomic_t *v, int new)
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{
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asm volatile(
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"1: r6 = memw_locked(%0);\n"
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" memw_locked(%0,p0) = %1;\n"
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" if (!P0) jump 1b;\n"
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:
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: "r" (&v->counter), "r" (new)
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: "memory", "p0", "r6"
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);
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}
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#define atomic_set_release(v, i) atomic_set((v), (i))
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/**
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* atomic_read - reads a word, atomically
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* @v: pointer to atomic value
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*
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* Assumes all word reads on our architecture are atomic.
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*/
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#define atomic_read(v) READ_ONCE((v)->counter)
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/**
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* atomic_xchg - atomic
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* @v: pointer to memory to change
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* @new: new value (technically passed in a register -- see xchg)
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*/
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#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
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/**
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* atomic_cmpxchg - atomic compare-and-exchange values
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* @v: pointer to value to change
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* @old: desired old value to match
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* @new: new value to put in
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*
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* Parameters are then pointer, value-in-register, value-in-register,
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* and the output is the old value.
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*
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* Apparently this is complicated for archs that don't support
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* the memw_locked like we do (or it's broken or whatever).
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*
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* Kind of the lynchpin of the rest of the generically defined routines.
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* Remember V2 had that bug with dotnew predicate set by memw_locked.
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*
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* "old" is "expected" old val, __oldval is actual old value
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*/
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int __oldval;
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asm volatile(
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"1: %0 = memw_locked(%1);\n"
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" { P0 = cmp.eq(%0,%2);\n"
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" if (!P0.new) jump:nt 2f; }\n"
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" memw_locked(%1,P0) = %3;\n"
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" if (!P0) jump 1b;\n"
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"2:\n"
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: "=&r" (__oldval)
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: "r" (&v->counter), "r" (old), "r" (new)
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: "memory", "p0"
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);
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return __oldval;
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}
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#define ATOMIC_OP(op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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int output; \
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\
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__asm__ __volatile__ ( \
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"1: %0 = memw_locked(%1);\n" \
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" %0 = "#op "(%0,%2);\n" \
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" memw_locked(%1,P3)=%0;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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int output; \
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\
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__asm__ __volatile__ ( \
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"1: %0 = memw_locked(%1);\n" \
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" %0 = "#op "(%0,%2);\n" \
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" memw_locked(%1,P3)=%0;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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); \
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return output; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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int output, val; \
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\
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__asm__ __volatile__ ( \
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"1: %0 = memw_locked(%2);\n" \
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" %1 = "#op "(%0,%3);\n" \
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" memw_locked(%2,P3)=%1;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output), "=&r" (val) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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); \
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return output; \
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}
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(add)
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ATOMIC_OPS(sub)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(and)
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ATOMIC_OPS(or)
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ATOMIC_OPS(xor)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/**
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* atomic_fetch_add_unless - add unless the number is a given value
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* @v: pointer to value
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* @a: amount to add
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* @u: unless value is equal to u
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*
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* Returns old value.
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*
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*/
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static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int __oldval;
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register int tmp;
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asm volatile(
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"1: %0 = memw_locked(%2);"
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" {"
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" p3 = cmp.eq(%0, %4);"
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" if (p3.new) jump:nt 2f;"
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" %1 = add(%0, %3);"
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" }"
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" memw_locked(%2, p3) = %1;"
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" {"
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" if (!p3) jump 1b;"
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" }"
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"2:"
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: "=&r" (__oldval), "=&r" (tmp)
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: "r" (v), "r" (a), "r" (u)
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: "memory", "p3"
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);
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return __oldval;
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}
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#define atomic_fetch_add_unless atomic_fetch_add_unless
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#endif
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