119 lines
4.0 KiB
Plaintext
119 lines
4.0 KiB
Plaintext
STMicroelectronics STM32 USB HS PHY controller
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The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
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switch. It controls PHY configuration and status, and the UTMI+ switch that
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selects either OTG or HOST controller for the second PHY port. It also sets
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PLL configuration.
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USBPHYC
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|_ PLL
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|_ PHY port#1 _________________ HOST controller
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| _ |
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| / 1|________________|
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|_ PHY port#2 ----| |________________
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| \_0| |
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|_ UTMI switch_______| OTG controller
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Phy provider node
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=================
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Required properties:
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- compatible: must be "st,stm32mp1-usbphyc"
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- reg: address and length of the usb phy control register set
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- clocks: phandle + clock specifier for the PLL phy clock
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- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
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- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
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- #address-cells: number of address cells for phys sub-nodes, must be <1>
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- #size-cells: number of size cells for phys sub-nodes, must be <0>
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- #clock-cells: number of clock cells for ck_usbo_48m consumer, must be <0>
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Optional properties:
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- assigned-clocks: phandle + clock specifier for the PLL phy clock
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- assigned-clock-parents: the PLL phy clock parent
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- resets: phandle + reset specifier
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Required nodes: one sub-node per port the controller provides.
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Phy sub-nodes
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=============
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Required properties:
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- reg: phy port index
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- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
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see phy-bindings.txt in the same directory.
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- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
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port#1 and must be <1> for PHY port#2, to select USB controller
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Optional properties:
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- st,phy-tuning : phandle to the usb phy tuning node, see Phy tuning node below
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Phy tuning node
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===============
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It may be necessary to adjust the phy settings to compensate parasitics, which
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can be due to USB connector/receptacle, routing, ESD protection component, ...
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Here is the list of all optional parameters to tune the interface of the phy
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(HS for High-Speed, FS for Full-Speed, LS for Low-Speed)
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Optional properties:
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- st,current-boost: <1> current boosting of 1mA
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<2> current boosting of 2mA
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- st,no-lsfs-fb-cap: disables the LS/FS feedback capacitor
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- st,hs-slew-ctrl: slows the HS driver slew rate by 10%
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- st,hs-dc-level: <0> decreases the HS driver DC level by 5 to 7mV
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<1> increases the HS driver DC level by 5 to 7mV
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<2> increases the HS driver DC level by 10 to 14mV
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- st,fs-rftime-tuning: enables the FS rise/fall tuning option
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- st,hs-rftime-reduction: enables the HS rise/fall reduction feature
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- st,hs-current-trim: controls HS driver current trimming for choke
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- st,hs-impedance-trim: controls HS driver impedance tuning for choke
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- st,squelch-level: adjusts the squelch DC threshold value
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- st,hs-rx-gain-eq: enables the HS Rx gain equalizer
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- st,hs-rx-offset: adjusts the HS Rx offset
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- st,no-hs-ftime-ctrl: disables the HS fall time control of single
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ended signals during pre-emphasis
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- st,no-lsfs-sc: disables the short circuit protection in LS/FS driver
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- st,hs-tx-staggering: enables the basic staggering in HS Tx mode
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Example:
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usb_phy_tuning: usb-phy-tuning {
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st,current-boost = <2>;
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st,no-lfs-fb-cap;
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st,hs-dc-level = <2>;
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st,hs-rftime-reduction;
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st,hs-current-trim = <5>;
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st,hs-impedance-trim = <0>;
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st,squelch-level = <1>;
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st,no-hs-ftime-ctrl;
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st,hs-tx-staggering;
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};
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usbphyc: usb-phy@5a006000 {
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compatible = "st,stm32mp1-usbphyc";
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reg = <0x5a006000 0x1000>;
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clocks = <&rcc_clk USBPHY_K>;
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resets = <&rcc_rst USBPHY_R>;
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vdda1v1-supply = <®11>;
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vdda1v8-supply = <®18>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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usbphyc_port0: usb-phy@0 {
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reg = <0>;
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phy-supply = <&vdd_usb>;
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#phy-cells = <0>;
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};
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usbphyc_port1: usb-phy@1 {
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reg = <1>;
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phy-supply = <&vdd_usb>;
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#phy-cells = <1>;
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st,phy-tuning = <&usb_phy_tuning>;
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};
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};
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